lauwal01 11c48370bd Workaround for Neoverse N1 erratum 1262888 ... Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>		2019-07-02 09:17:17 -05:00
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aarch32	cpus: Fix Cortex-A12 MIDR mask	2019-04-08 12:47:48 +02:00
aarch64	Workaround for Neoverse N1 erratum 1262888	2019-07-02 09:17:17 -05:00
errata_report.h	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
wa_cve_2017_5715.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00
wa_cve_2018_3639.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00