178 lines
4.2 KiB
ArmAsm
178 lines
4.2 KiB
ArmAsm
/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <cortex_a73.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* ---------------------------------------------
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* Disable L1 data cache
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* ---------------------------------------------
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*/
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func cortex_a73_disable_dcache
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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ret
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endfunc cortex_a73_disable_dcache
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* ---------------------------------------------
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*/
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func cortex_a73_disable_smp
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mrs x0, CORTEX_A73_CPUECTLR_EL1
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bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
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msr CORTEX_A73_CPUECTLR_EL1, x0
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isb
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dsb sy
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ret
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endfunc cortex_a73_disable_smp
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func cortex_a73_reset_func
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#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
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cpu_check_csv2 x0, 1f
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adr x0, workaround_bpiall_vbar0_runtime_exceptions
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msr vbar_el3, x0
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1:
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#endif
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/* ---------------------------------------------
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* Enable the SMP bit.
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* Clobbers : x0
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A73_CPUECTLR_EL1
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orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
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msr CORTEX_A73_CPUECTLR_EL1, x0
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isb
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ret
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endfunc cortex_a73_reset_func
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func cortex_a73_core_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a73_disable_dcache
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a73_disable_smp
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endfunc cortex_a73_core_pwr_dwn
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func cortex_a73_cluster_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a73_disable_dcache
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* ---------------------------------------------
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* Flush L2 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a73_disable_smp
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endfunc cortex_a73_cluster_pwr_dwn
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func check_errata_cve_2017_5715
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cpu_check_csv2 x0, 1f
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#if WORKAROUND_CVE_2017_5715
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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1:
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mov x0, #ERRATA_NOT_APPLIES
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ret
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endfunc check_errata_cve_2017_5715
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A75. Must follow AAPCS.
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*/
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func cortex_a73_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a73_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cortex_a73 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a73_regs, "aS"
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cortex_a73_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", "l2merrsr_el1", ""
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func cortex_a73_cpu_reg_dump
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adr x6, cortex_a73_regs
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mrs x8, CORTEX_A73_CPUECTLR_EL1
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mrs x9, CORTEX_A73_L2MERRSR_EL1
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ret
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endfunc cortex_a73_cpu_reg_dump
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declare_cpu_ops_workaround_cve_2017_5715 cortex_a73, CORTEX_A73_MIDR, \
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cortex_a73_reset_func, \
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check_errata_cve_2017_5715, \
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cortex_a73_core_pwr_dwn, \
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cortex_a73_cluster_pwr_dwn
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