246 lines
8.7 KiB
C
246 lines
8.7 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <bl31.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <platform.h>
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#include <runtime_svc.h>
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/*******************************************************************************
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* Data structure which holds the pointers to non-secure and secure security
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* state contexts for each cpu. It is aligned to the cache line boundary to
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* allow efficient concurrent manipulation of these pointers on different cpus
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******************************************************************************/
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typedef struct {
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void *ptr[2];
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} __aligned (CACHE_WRITEBACK_GRANULE) context_info_t;
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static context_info_t cm_context_info[PLATFORM_CORE_COUNT];
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/* The per_cpu_ptr_cache_t space allocation */
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static per_cpu_ptr_cache_t per_cpu_ptr_cache_space[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* Context management library initialisation routine. This library is used by
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* runtime services to share pointers to 'cpu_context' structures for the secure
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* and non-secure states. Management of the structures and their associated
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* memory is not done by the context management library e.g. the PSCI service
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* manages the cpu context used for entry from and exit to the non-secure state.
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* The Secure payload dispatcher service manages the context(s) corresponding to
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* the secure state. It also uses this library to get access to the non-secure
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* state cpu context pointers.
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* Lastly, this library provides the api to make SP_EL3 point to the cpu context
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* which will used for programming an entry into a lower EL. The same context
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* will used to save state upon exception entry from that EL.
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******************************************************************************/
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void cm_init()
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{
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/*
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* The context management library has only global data to intialize, but
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* that will be done when the BSS is zeroed out
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*/
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}
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/*******************************************************************************
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* This function returns a pointer to the most recent 'cpu_context' structure
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* that was set as the context for the specified security state. NULL is
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* returned if no such structure has been specified.
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******************************************************************************/
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void *cm_get_context(uint64_t mpidr, uint32_t security_state)
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{
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uint32_t linear_id = platform_get_core_pos(mpidr);
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assert(security_state <= NON_SECURE);
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return cm_context_info[linear_id].ptr[security_state];
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}
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/*******************************************************************************
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* This function sets the pointer to the current 'cpu_context' structure for the
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* specified security state.
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******************************************************************************/
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void cm_set_context(uint64_t mpidr, void *context, uint32_t security_state)
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{
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uint32_t linear_id = platform_get_core_pos(mpidr);
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assert(security_state <= NON_SECURE);
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cm_context_info[linear_id].ptr[security_state] = context;
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}
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/*******************************************************************************
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* The next four functions are used by runtime services to save and restore EL3
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* and EL1 contexts on the 'cpu_context' structure for the specified security
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* state.
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******************************************************************************/
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void cm_el3_sysregs_context_save(uint32_t security_state)
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{
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cpu_context_t *ctx;
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ctx = cm_get_context(read_mpidr(), security_state);
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assert(ctx);
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el3_sysregs_context_save(get_el3state_ctx(ctx));
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}
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void cm_el3_sysregs_context_restore(uint32_t security_state)
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{
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cpu_context_t *ctx;
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ctx = cm_get_context(read_mpidr(), security_state);
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assert(ctx);
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el3_sysregs_context_restore(get_el3state_ctx(ctx));
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}
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void cm_el1_sysregs_context_save(uint32_t security_state)
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{
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cpu_context_t *ctx;
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ctx = cm_get_context(read_mpidr(), security_state);
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assert(ctx);
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el1_sysregs_context_save(get_sysregs_ctx(ctx));
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}
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void cm_el1_sysregs_context_restore(uint32_t security_state)
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{
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cpu_context_t *ctx;
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ctx = cm_get_context(read_mpidr(), security_state);
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assert(ctx);
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el1_sysregs_context_restore(get_sysregs_ctx(ctx));
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}
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/*******************************************************************************
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* This function function populates 'cpu_context' pertaining to the given
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* security state with the entrypoint, SPSR and SCR values so that an ERET from
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* this securit state correctly restores corresponding values to drop the CPU to
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* the next exception level
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******************************************************************************/
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void cm_set_el3_eret_context(uint32_t security_state, uint64_t entrypoint,
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uint32_t spsr, uint32_t scr)
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{
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cpu_context_t *ctx;
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el3_state_t *state;
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ctx = cm_get_context(read_mpidr(), security_state);
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assert(ctx);
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/* Populate EL3 state so that we've the right context before doing ERET */
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state = get_el3state_ctx(ctx);
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write_ctx_reg(state, CTX_SPSR_EL3, spsr);
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write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
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write_ctx_reg(state, CTX_SCR_EL3, scr);
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}
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/*******************************************************************************
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* This function function populates ELR_EL3 member of 'cpu_context' pertaining
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* to the given security state with the given entrypoint
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******************************************************************************/
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void cm_set_el3_elr(uint32_t security_state, uint64_t entrypoint)
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{
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cpu_context_t *ctx;
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el3_state_t *state;
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ctx = cm_get_context(read_mpidr(), security_state);
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assert(ctx);
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/* Populate EL3 state so that ERET jumps to the correct entry */
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state = get_el3state_ctx(ctx);
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write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
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}
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/*******************************************************************************
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* This function is used to program the context that's used for exception
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* return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
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* the required security state
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******************************************************************************/
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void cm_set_next_eret_context(uint32_t security_state)
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{
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cpu_context_t *ctx;
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#if DEBUG
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uint64_t sp_mode;
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#endif
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ctx = cm_get_context(read_mpidr(), security_state);
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assert(ctx);
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#if DEBUG
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/*
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* Check that this function is called with SP_EL0 as the stack
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* pointer
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*/
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__asm__ volatile("mrs %0, SPSel\n"
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: "=r" (sp_mode));
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assert(sp_mode == MODE_SP_EL0);
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#endif
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__asm__ volatile("msr spsel, #1\n"
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"mov sp, %0\n"
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"msr spsel, #0\n"
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: : "r" (ctx));
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}
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/************************************************************************
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* The following function is used to populate the per cpu pointer cache.
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* The pointer will be stored in the tpidr_el3 register.
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*************************************************************************/
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void cm_init_pcpu_ptr_cache()
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{
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unsigned long mpidr = read_mpidr();
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uint32_t linear_id = platform_get_core_pos(mpidr);
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per_cpu_ptr_cache_t *pcpu_ptr_cache;
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pcpu_ptr_cache = &per_cpu_ptr_cache_space[linear_id];
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assert(pcpu_ptr_cache);
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pcpu_ptr_cache->crash_stack = get_crash_stack(mpidr);
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cm_set_pcpu_ptr_cache(pcpu_ptr_cache);
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}
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void cm_set_pcpu_ptr_cache(const void *pcpu_ptr)
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{
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write_tpidr_el3((unsigned long)pcpu_ptr);
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}
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void *cm_get_pcpu_ptr_cache(void)
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{
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return (void *)read_tpidr_el3();
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}
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