159 lines
4.0 KiB
C
159 lines
4.0 KiB
C
/*
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* Copyright (c) 2019, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* common headers */
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#include <arch_helpers.h>
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#include <assert.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <errno.h>
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/* mediatek platform specific headers */
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#include <platform_def.h>
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#include <scu.h>
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#include <mt_gic_v3.h>
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#include <mtk_plat_common.h>
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#include <mtspmc.h>
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#include <power_tracer.h>
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#include <plat_dcm.h>
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#include <plat_debug.h>
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#include <plat_private.h>
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#include <pmic.h>
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#include <rtc.h>
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#define MTK_LOCAL_STATE_OFF 2
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static uintptr_t secure_entrypoint;
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static void mp1_L2_desel_config(void)
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{
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mmio_write_64(MCUCFG_BASE + 0x2200, 0x2092c820);
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dsb();
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}
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static int plat_mtk_power_domain_on(unsigned long mpidr)
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{
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int cpu = MPIDR_AFFLVL0_VAL(mpidr);
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int cluster = MPIDR_AFFLVL1_VAL(mpidr);
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INFO("%s():%d: mpidr: %lx, c.c: %d.%d\n",
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__func__, __LINE__, mpidr, cluster, cpu);
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/* power on cluster */
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if (!spm_get_cluster_powerstate(cluster)) {
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spm_poweron_cluster(cluster);
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if (cluster == 1) {
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l2c_parity_check_setup();
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circular_buffer_setup();
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mp1_L2_desel_config();
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mt_gic_sync_dcm_disable();
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}
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}
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/* init cpu reset arch as AARCH64 */
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mcucfg_init_archstate(cluster, cpu, 1);
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mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
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spm_poweron_cpu(cluster, cpu);
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return PSCI_E_SUCCESS;
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}
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static void plat_mtk_power_domain_off(const psci_power_state_t *state)
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{
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uint64_t mpidr = read_mpidr();
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int cpu = MPIDR_AFFLVL0_VAL(mpidr);
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int cluster = MPIDR_AFFLVL1_VAL(mpidr);
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INFO("%s():%d: c.c: %d.%d\n", __func__, __LINE__, cluster, cpu);
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/* Prevent interrupts from spuriously waking up this cpu */
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mt_gic_cpuif_disable();
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spm_enable_cpu_auto_off(cluster, cpu);
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if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) {
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if (cluster == 1)
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mt_gic_sync_dcm_enable();
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plat_mtk_cci_disable();
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spm_enable_cluster_auto_off(cluster);
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}
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spm_set_cpu_power_off(cluster, cpu);
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}
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static void plat_mtk_power_domain_on_finish(const psci_power_state_t *state)
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{
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uint64_t mpidr = read_mpidr();
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int cpu = MPIDR_AFFLVL0_VAL(mpidr);
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int cluster = MPIDR_AFFLVL1_VAL(mpidr);
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INFO("%s():%d: c.c: %d.%d\n", __func__, __LINE__, cluster, cpu);
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assert(state->pwr_domain_state[MPIDR_AFFLVL0] == MTK_LOCAL_STATE_OFF);
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if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) {
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enable_scu(mpidr);
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/* Enable coherency if this cluster was off */
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plat_mtk_cci_enable();
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/* Enable big core dcm if this cluster was on */
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plat_dcm_restore_cluster_on(mpidr);
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/* Enable rgu dcm if this cluster was off */
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plat_dcm_rgu_enable();
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}
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spm_disable_cpu_auto_off(cluster, cpu);
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/* Enable the gic cpu interface */
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mt_gic_pcpu_init();
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mt_gic_cpuif_enable();
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}
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/*******************************************************************************
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* MTK handlers to shutdown/reboot the system
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******************************************************************************/
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static void __dead2 plat_mtk_system_off(void)
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{
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INFO("MTK System Off\n");
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rtc_power_off_sequence();
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wk_pmic_enable_sdn_delay();
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pmic_power_off();
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wfi();
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ERROR("MTK System Off: operation not handled.\n");
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panic();
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}
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/*******************************************************************************
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* MTK_platform handler called when an affinity instance is about to be turned
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* on. The level and mpidr determine the affinity instance.
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******************************************************************************/
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static const plat_psci_ops_t plat_plat_pm_ops = {
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.cpu_standby = NULL,
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.pwr_domain_on = plat_mtk_power_domain_on,
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.pwr_domain_on_finish = plat_mtk_power_domain_on_finish,
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.pwr_domain_off = plat_mtk_power_domain_off,
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.pwr_domain_suspend = NULL,
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.pwr_domain_suspend_finish = NULL,
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.system_off = plat_mtk_system_off,
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.system_reset = NULL,
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.validate_power_state = NULL,
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.get_sys_suspend_power_state = NULL,
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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*psci_ops = &plat_plat_pm_ops;
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secure_entrypoint = sec_entrypoint;
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return 0;
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}
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