132 lines
3.7 KiB
ArmAsm
132 lines
3.7 KiB
ArmAsm
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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.globl smc
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.globl zeromem
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.globl memcpy4
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.globl disable_mmu_icache_secure
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.globl disable_mmu_secure
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func smc
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/*
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* For AArch32 only r0-r3 will be in the registers;
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* rest r4-r6 will be pushed on to the stack. So here, we'll
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* have to load them from the stack to registers r4-r6 explicitly.
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* Clobbers: r4-r6
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*/
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ldm sp, {r4, r5, r6}
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smc #0
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endfunc smc
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/* -----------------------------------------------------------------------
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* void zeromem(void *mem, unsigned int length);
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*
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* Initialise a memory region to 0.
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* The memory address and length must be 4-byte aligned.
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* -----------------------------------------------------------------------
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*/
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func zeromem
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#if ASM_ASSERTION
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tst r0, #0x3
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ASM_ASSERT(eq)
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tst r1, #0x3
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ASM_ASSERT(eq)
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#endif
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add r2, r0, r1
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mov r1, #0
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z_loop:
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cmp r2, r0
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beq z_end
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str r1, [r0], #4
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b z_loop
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z_end:
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bx lr
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endfunc zeromem
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/* --------------------------------------------------------------------------
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* void memcpy4(void *dest, const void *src, unsigned int length)
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*
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* Copy length bytes from memory area src to memory area dest.
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* The memory areas should not overlap.
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* Destination and source addresses must be 4-byte aligned.
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* --------------------------------------------------------------------------
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*/
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func memcpy4
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#if ASM_ASSERTION
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orr r3, r0, r1
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tst r3, #0x3
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ASM_ASSERT(eq)
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#endif
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/* copy 4 bytes at a time */
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m_loop4:
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cmp r2, #4
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blt m_loop1
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ldr r3, [r1], #4
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str r3, [r0], #4
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sub r2, r2, #4
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b m_loop4
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/* copy byte per byte */
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m_loop1:
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cmp r2,#0
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beq m_end
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ldrb r3, [r1], #1
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strb r3, [r0], #1
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subs r2, r2, #1
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bne m_loop1
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m_end:
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bx lr
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endfunc memcpy4
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/* ---------------------------------------------------------------------------
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* Disable the MMU in Secure State
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* ---------------------------------------------------------------------------
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*/
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func disable_mmu_secure
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mov r1, #(SCTLR_M_BIT | SCTLR_C_BIT)
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do_disable_mmu:
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ldcopr r0, SCTLR
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bic r0, r0, r1
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stcopr r0, SCTLR
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isb // ensure MMU is off
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dsb sy
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bx lr
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endfunc disable_mmu_secure
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func disable_mmu_icache_secure
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ldr r1, =(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
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b do_disable_mmu
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endfunc disable_mmu_icache_secure
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