130 lines
4.3 KiB
C
130 lines
4.3 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arm_def.h>
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#include <gicv3.h>
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#include <plat_arm.h>
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#include <platform.h>
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#include <platform_def.h>
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/******************************************************************************
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* The following functions are defined as weak to allow a platform to override
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* the way the GICv3 driver is initialised and used.
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*****************************************************************************/
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#pragma weak plat_arm_gic_driver_init
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#pragma weak plat_arm_gic_init
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#pragma weak plat_arm_gic_cpuif_enable
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#pragma weak plat_arm_gic_cpuif_disable
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#pragma weak plat_arm_gic_pcpu_init
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#pragma weak plat_arm_gic_redistif_on
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#pragma weak plat_arm_gic_redistif_off
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/* The GICv3 driver only needs to be initialized in EL3 */
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static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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/* Array of Group1 secure interrupts to be configured by the gic driver */
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static const unsigned int g1s_interrupt_array[] = {
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PLAT_ARM_G1S_IRQS
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};
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/* Array of Group0 interrupts to be configured by the gic driver */
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static const unsigned int g0_interrupt_array[] = {
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PLAT_ARM_G0_IRQS
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};
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/*
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* MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
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* to core position.
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*
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* Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
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* values read from GICR_TYPER don't have an MT field. To reuse the same
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* translation used for CPUs, we insert MT bit read from the PE's MPIDR into
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* that read from GICR_TYPER.
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*
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* Assumptions:
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*
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* - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
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* - No CPUs implemented in the system use affinity level 3.
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*/
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static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr)
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{
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mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
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return plat_arm_calc_core_pos(mpidr);
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}
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const gicv3_driver_data_t arm_gic_data = {
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.gicd_base = PLAT_ARM_GICD_BASE,
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.gicr_base = PLAT_ARM_GICR_BASE,
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.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
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.g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
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.g0_interrupt_array = g0_interrupt_array,
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.g1s_interrupt_array = g1s_interrupt_array,
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = rdistif_base_addrs,
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.mpidr_to_core_pos = arm_gicv3_mpidr_hash
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};
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void plat_arm_gic_driver_init(void)
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{
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/*
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* The GICv3 driver is initialized in EL3 and does not need
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* to be initialized again in SEL1. This is because the S-EL1
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* can use GIC system registers to manage interrupts and does
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* not need GIC interface base addresses to be configured.
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*/
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#if (defined(AARCH32) && defined(IMAGE_BL32)) || \
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(defined(IMAGE_BL31) && !defined(AARCH32))
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gicv3_driver_init(&arm_gic_data);
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#endif
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}
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/******************************************************************************
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* ARM common helper to initialize the GIC. Only invoked by BL31
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*****************************************************************************/
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void plat_arm_gic_init(void)
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{
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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/******************************************************************************
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* ARM common helper to enable the GIC CPU interface
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*****************************************************************************/
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void plat_arm_gic_cpuif_enable(void)
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{
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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/******************************************************************************
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* ARM common helper to disable the GIC CPU interface
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*****************************************************************************/
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void plat_arm_gic_cpuif_disable(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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}
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/******************************************************************************
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* ARM common helper to initialize the per-cpu redistributor interface in GICv3
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*****************************************************************************/
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void plat_arm_gic_pcpu_init(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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}
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/******************************************************************************
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* ARM common helpers to power GIC redistributor interface
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*****************************************************************************/
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void plat_arm_gic_redistif_on(void)
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{
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gicv3_rdistif_on(plat_my_core_pos());
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}
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void plat_arm_gic_redistif_off(void)
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{
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gicv3_rdistif_off(plat_my_core_pos());
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}
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