Louis Mayencourt 2fc18a25f5 plat/sgi: Bump bl1 RW limit ... Increase bl1 RW limit to allow future development. Change-Id: I3159b36dbaca798b4c4374c1415cd033d6586388 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>		2020-03-13 10:40:57 +00:00
..
aarch64	plat/arm/sgi: include AFF3 affinity in core position calculation	2020-02-07 19:24:17 +05:30
include	plat/sgi: Bump bl1 RW limit	2020-03-13 10:40:57 +00:00
sgi-common.mk	TF-A GICv3 driver: Separate GICD and GICR accessor functions	2020-03-10 09:40:19 +00:00
sgi_bl31_setup.c	plat/arm: add board support for rd-daniel platform	2020-02-07 19:24:17 +05:30
sgi_image_load.c	platform/arm/sgi: add multi-chip mode parameter in HW_CONFIG dts	2020-02-07 19:24:17 +05:30
sgi_interconnect.c	Remove several warnings reported with W=1	2019-04-01 10:43:42 +01:00
sgi_plat.c	spm-mm: Refactor secure_partition.h and its contents	2019-12-20 16:03:41 +00:00
sgi_ras.c	spm-mm: Remove mm_svc.h header	2019-12-20 16:04:01 +00:00
sgi_topology.c	plat/arm/sgi: move topology information to board folder	2020-01-27 19:54:05 +05:30