822 lines
16 KiB
C
822 lines
16 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PMU_H__
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#define __PMU_H__
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/* Allocate sp reginon in pmusram */
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#define PSRAM_SP_SIZE 0x80
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#define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE)
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/*****************************************************************************
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* Common define for per soc pmu.h
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*****************************************************************************/
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/* The ways of cores power domain contorlling */
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enum cores_pm_ctr_mode {
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core_pwr_pd = 0,
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core_pwr_wfi = 1,
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core_pwr_wfi_int = 2
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};
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/*****************************************************************************
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* pmu con,reg
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*****************************************************************************/
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#define PMU_WKUP_CFG(n) ((n) * 4)
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#define PMU_CORE_PM_CON(cpu) (0xc0 + (cpu * 4))
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/* the shift of bits for cores status */
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enum pmu_core_pwrst_shift {
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clstl_cpu_wfe = 2,
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clstl_cpu_wfi = 6,
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clstb_cpu_wfe = 12,
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clstb_cpu_wfi = 16
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};
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#define CKECK_WFE_MSK 0x1
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#define CKECK_WFI_MSK 0x10
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#define CKECK_WFEI_MSK 0x11
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enum pmu_powerdomain_id {
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PD_CPUL0 = 0,
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PD_CPUL1,
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PD_CPUL2,
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PD_CPUL3,
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PD_CPUB0,
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PD_CPUB1,
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PD_SCUL,
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PD_SCUB,
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PD_TCPD0,
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PD_TCPD1,
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PD_CCI,
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PD_PERILP,
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PD_PERIHP,
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PD_CENTER,
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PD_VIO,
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PD_GPU,
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PD_VCODEC,
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PD_VDU,
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PD_RGA,
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PD_IEP,
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PD_VO,
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PD_ISP0 = 22,
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PD_ISP1,
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PD_HDCP,
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PD_GMAC,
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PD_EMMC,
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PD_USB3,
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PD_EDP,
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PD_GIC,
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PD_SD,
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PD_SDIOAUDIO,
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PD_END
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};
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enum powerdomain_state {
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PMU_POWER_ON = 0,
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PMU_POWER_OFF,
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};
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enum pmu_bus_id {
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BUS_ID_GPU = 0,
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BUS_ID_PERILP,
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BUS_ID_PERIHP,
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BUS_ID_VCODEC,
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BUS_ID_VDU,
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BUS_ID_RGA,
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BUS_ID_IEP,
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BUS_ID_VOPB,
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BUS_ID_VOPL,
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BUS_ID_ISP0,
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BUS_ID_ISP1,
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BUS_ID_HDCP,
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BUS_ID_USB3,
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BUS_ID_PERILPM0,
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BUS_ID_CENTER,
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BUS_ID_CCIM0,
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BUS_ID_CCIM1,
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BUS_ID_VIO,
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BUS_ID_MSCH0,
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BUS_ID_MSCH1,
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BUS_ID_ALIVE,
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BUS_ID_PMU,
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BUS_ID_EDP,
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BUS_ID_GMAC,
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BUS_ID_EMMC,
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BUS_ID_CENTER1,
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BUS_ID_PMUM0,
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BUS_ID_GIC,
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BUS_ID_SD,
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BUS_ID_SDIOAUDIO,
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};
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enum pmu_bus_state {
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BUS_ACTIVE,
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BUS_IDLE,
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};
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/* pmu_cpuapm bit */
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enum pmu_cores_pm_by_wfi {
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core_pm_en = 0,
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core_pm_int_wakeup_en,
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core_pm_resv,
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core_pm_sft_wakeup_en
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};
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enum pmu_wkup_cfg0 {
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PMU_GPIO0A_POSE_WKUP_EN = 0,
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PMU_GPIO0B_POSE_WKUP_EN = 8,
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PMU_GPIO0C_POSE_WKUP_EN = 16,
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PMU_GPIO0D_POSE_WKUP_EN = 24,
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};
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enum pmu_wkup_cfg1 {
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PMU_GPIO0A_NEGEDGE_WKUP_EN = 0,
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PMU_GPIO0B_NEGEDGE_WKUP_EN = 7,
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PMU_GPIO0C_NEGEDGE_WKUP_EN = 16,
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PMU_GPIO0D_NEGEDGE_WKUP_EN = 24,
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};
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enum pmu_wkup_cfg2 {
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PMU_GPIO1A_POSE_WKUP_EN = 0,
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PMU_GPIO1B_POSE_WKUP_EN = 7,
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PMU_GPIO1C_POSE_WKUP_EN = 16,
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PMU_GPIO1D_POSE_WKUP_EN = 24,
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};
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enum pmu_wkup_cfg3 {
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PMU_GPIO1A_NEGEDGE_WKUP_EN = 0,
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PMU_GPIO1B_NEGEDGE_WKUP_EN = 7,
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PMU_GPIO1C_NEGEDGE_WKUP_EN = 16,
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PMU_GPIO1D_NEGEDGE_WKUP_EN = 24,
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};
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/* pmu_wkup_cfg4 */
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enum pmu_wkup_cfg4 {
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PMU_CLUSTER_L_WKUP_EN = 0,
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PMU_CLUSTER_B_WKUP_EN,
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PMU_GPIO_WKUP_EN,
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PMU_SDIO_WKUP_EN,
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PMU_SDMMC_WKUP_EN,
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PMU_TIMER_WKUP_EN = 6,
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PMU_USBDEV_WKUP_EN,
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PMU_SFT_WKUP_EN,
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PMU_M0_WDT_WKUP_EN,
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PMU_TIMEOUT_WKUP_EN,
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PMU_PWM_WKUP_EN,
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PMU_PCIE_WKUP_EN = 13,
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};
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enum pmu_pwrdn_con {
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PMU_A53_L0_PWRDWN_EN = 0,
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PMU_A53_L1_PWRDWN_EN,
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PMU_A53_L2_PWRDWN_EN,
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PMU_A53_L3_PWRDWN_EN,
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PMU_A72_B0_PWRDWN_EN,
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PMU_A72_B1_PWRDWN_EN,
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PMU_SCU_L_PWRDWN_EN,
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PMU_SCU_B_PWRDWN_EN,
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PMU_TCPD0_PWRDWN_EN,
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PMU_TCPD1_PWRDWN_EN,
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PMU_CCI_PWRDWN_EN,
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PMU_PERILP_PWRDWN_EN,
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PMU_PERIHP_PWRDWN_EN,
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PMU_CENTER_PWRDWN_EN,
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PMU_VIO_PWRDWN_EN,
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PMU_GPU_PWRDWN_EN,
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PMU_VCODEC_PWRDWN_EN,
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PMU_VDU_PWRDWN_EN,
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PMU_RGA_PWRDWN_EN,
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PMU_IEP_PWRDWN_EN,
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PMU_VO_PWRDWN_EN,
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PMU_ISP0_PWRDWN_EN = 22,
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PMU_ISP1_PWRDWN_EN,
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PMU_HDCP_PWRDWN_EN,
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PMU_GMAC_PWRDWN_EN,
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PMU_EMMC_PWRDWN_EN,
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PMU_USB3_PWRDWN_EN,
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PMU_EDP_PWRDWN_EN,
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PMU_GIC_PWRDWN_EN,
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PMU_SD_PWRDWN_EN,
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PMU_SDIOAUDIO_PWRDWN_EN,
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};
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enum pmu_pwrdn_st {
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PMU_A53_L0_PWRDWN_ST = 0,
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PMU_A53_L1_PWRDWN_ST,
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PMU_A53_L2_PWRDWN_ST,
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PMU_A53_L3_PWRDWN_ST,
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PMU_A72_B0_PWRDWN_ST,
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PMU_A72_B1_PWRDWN_ST,
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PMU_SCU_L_PWRDWN_ST,
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PMU_SCU_B_PWRDWN_ST,
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PMU_TCPD0_PWRDWN_ST,
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PMU_TCPD1_PWRDWN_ST,
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PMU_CCI_PWRDWN_ST,
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PMU_PERILP_PWRDWN_ST,
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PMU_PERIHP_PWRDWN_ST,
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PMU_CENTER_PWRDWN_ST,
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PMU_VIO_PWRDWN_ST,
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PMU_GPU_PWRDWN_ST,
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PMU_VCODEC_PWRDWN_ST,
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PMU_VDU_PWRDWN_ST,
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PMU_RGA_PWRDWN_ST,
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PMU_IEP_PWRDWN_ST,
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PMU_VO_PWRDWN_ST,
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PMU_ISP0_PWRDWN_ST = 22,
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PMU_ISP1_PWRDWN_ST,
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PMU_HDCP_PWRDWN_ST,
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PMU_GMAC_PWRDWN_ST,
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PMU_EMMC_PWRDWN_ST,
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PMU_USB3_PWRDWN_ST,
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PMU_EDP_PWRDWN_ST,
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PMU_GIC_PWRDWN_ST,
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PMU_SD_PWRDWN_ST,
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PMU_SDIOAUDIO_PWRDWN_ST,
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};
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enum pmu_pll_con {
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PMU_PLL_PD_CFG = 0,
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PMU_SFT_PLL_PD = 8,
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};
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enum pmu_pwermode_con {
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PMU_PWR_MODE_EN = 0,
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PMU_WKUP_RST_EN,
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PMU_INPUT_CLAMP_EN,
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PMU_OSC_DIS,
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PMU_ALIVE_USE_LF,
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PMU_PMU_USE_LF,
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PMU_POWER_OFF_REQ_CFG,
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PMU_CHIP_PD_EN,
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PMU_PLL_PD_EN,
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PMU_CPU0_PD_EN,
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PMU_L2_FLUSH_EN,
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PMU_L2_IDLE_EN,
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PMU_SCU_PD_EN,
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PMU_CCI_PD_EN,
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PMU_PERILP_PD_EN,
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PMU_CENTER_PD_EN,
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PMU_SREF0_ENTER_EN,
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PMU_DDRC0_GATING_EN,
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PMU_DDRIO0_RET_EN,
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PMU_DDRIO0_RET_DE_REQ,
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PMU_SREF1_ENTER_EN,
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PMU_DDRC1_GATING_EN,
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PMU_DDRIO1_RET_EN,
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PMU_DDRIO1_RET_DE_REQ,
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PMU_CLK_CENTER_SRC_GATE_EN = 26,
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PMU_CLK_PERILP_SRC_GATE_EN,
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PMU_CLK_CORE_SRC_GATE_EN,
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PMU_DDRIO_RET_HW_DE_REQ,
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PMU_SLP_OUTPUT_CFG,
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PMU_MAIN_CLUSTER,
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};
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enum pmu_sft_con {
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PMU_WKUP_SFT = 0,
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PMU_INPUT_CLAMP_CFG,
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PMU_OSC_DIS_CFG,
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PMU_PMU_LF_EN_CFG,
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PMU_ALIVE_LF_EN_CFG,
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PMU_24M_EN_CFG,
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PMU_DBG_PWRUP_L0_CFG,
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PMU_WKUP_SFT_M0,
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PMU_DDRCTL0_C_SYSREQ_CFG,
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PMU_DDR0_IO_RET_CFG,
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PMU_DDRCTL1_C_SYSREQ_CFG = 12,
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PMU_DDR1_IO_RET_CFG,
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DBG_PWRUP_B0_CFG = 15,
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DBG_NOPWERDWN_L0_EN,
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DBG_NOPWERDWN_L1_EN,
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DBG_NOPWERDWN_L2_EN,
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DBG_NOPWERDWN_L3_EN,
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DBG_PWRUP_REQ_L_EN = 20,
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CLUSTER_L_CLK_SRC_GATING_CFG,
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L2_FLUSH_REQ_CLUSTER_L,
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ACINACTM_CLUSTER_L_CFG,
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DBG_NO_PWERDWN_B0_EN,
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DBG_NO_PWERDWN_B1_EN,
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DBG_PWRUP_REQ_B_EN = 28,
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CLUSTER_B_CLK_SRC_GATING_CFG,
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L2_FLUSH_REQ_CLUSTER_B,
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ACINACTM_CLUSTER_B_CFG,
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};
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enum pmu_int_con {
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PMU_PMU_INT_EN = 0,
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PMU_PWRMD_WKUP_INT_EN,
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PMU_WKUP_GPIO0_NEG_INT_EN,
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PMU_WKUP_GPIO0_POS_INT_EN,
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PMU_WKUP_GPIO1_NEG_INT_EN,
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PMU_WKUP_GPIO1_POS_INT_EN,
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};
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enum pmu_int_st {
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PMU_PWRMD_WKUP_INT_ST = 1,
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PMU_WKUP_GPIO0_NEG_INT_ST,
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PMU_WKUP_GPIO0_POS_INT_ST,
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PMU_WKUP_GPIO1_NEG_INT_ST,
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PMU_WKUP_GPIO1_POS_INT_ST,
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};
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enum pmu_gpio0_pos_int_con {
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PMU_GPIO0A_POS_INT_EN = 0,
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PMU_GPIO0B_POS_INT_EN = 8,
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PMU_GPIO0C_POS_INT_EN = 16,
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PMU_GPIO0D_POS_INT_EN = 24,
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};
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enum pmu_gpio0_neg_int_con {
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PMU_GPIO0A_NEG_INT_EN = 0,
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PMU_GPIO0B_NEG_INT_EN = 8,
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PMU_GPIO0C_NEG_INT_EN = 16,
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PMU_GPIO0D_NEG_INT_EN = 24,
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};
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enum pmu_gpio1_pos_int_con {
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PMU_GPIO1A_POS_INT_EN = 0,
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PMU_GPIO1B_POS_INT_EN = 8,
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PMU_GPIO1C_POS_INT_EN = 16,
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PMU_GPIO1D_POS_INT_EN = 24,
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};
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enum pmu_gpio1_neg_int_con {
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PMU_GPIO1A_NEG_INT_EN = 0,
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PMU_GPIO1B_NEG_INT_EN = 8,
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PMU_GPIO1C_NEG_INT_EN = 16,
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PMU_GPIO1D_NEG_INT_EN = 24,
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};
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enum pmu_gpio0_pos_int_st {
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PMU_GPIO0A_POS_INT_ST = 0,
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PMU_GPIO0B_POS_INT_ST = 8,
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PMU_GPIO0C_POS_INT_ST = 16,
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PMU_GPIO0D_POS_INT_ST = 24,
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};
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enum pmu_gpio0_neg_int_st {
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PMU_GPIO0A_NEG_INT_ST = 0,
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PMU_GPIO0B_NEG_INT_ST = 8,
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PMU_GPIO0C_NEG_INT_ST = 16,
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PMU_GPIO0D_NEG_INT_ST = 24,
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};
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enum pmu_gpio1_pos_int_st {
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PMU_GPIO1A_POS_INT_ST = 0,
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PMU_GPIO1B_POS_INT_ST = 8,
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PMU_GPIO1C_POS_INT_ST = 16,
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PMU_GPIO1D_POS_INT_ST = 24,
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};
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enum pmu_gpio1_neg_int_st {
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PMU_GPIO1A_NEG_INT_ST = 0,
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PMU_GPIO1B_NEG_INT_ST = 8,
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PMU_GPIO1C_NEG_INT_ST = 16,
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PMU_GPIO1D_NEG_INT_ST = 24,
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};
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/* pmu power down configure register 0x0050 */
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enum pmu_pwrdn_inten {
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PMU_A53_L0_PWR_SWITCH_INT_EN = 0,
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PMU_A53_L1_PWR_SWITCH_INT_EN,
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PMU_A53_L2_PWR_SWITCH_INT_EN,
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PMU_A53_L3_PWR_SWITCH_INT_EN,
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PMU_A72_B0_PWR_SWITCH_INT_EN,
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PMU_A72_B1_PWR_SWITCH_INT_EN,
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PMU_SCU_L_PWR_SWITCH_INT_EN,
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PMU_SCU_B_PWR_SWITCH_INT_EN,
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PMU_TCPD0_PWR_SWITCH_INT_EN,
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PMU_TCPD1_PWR_SWITCH_INT_EN,
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PMU_CCI_PWR_SWITCH_INT_EN,
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PMU_PERILP_PWR_SWITCH_INT_EN,
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PMU_PERIHP_PWR_SWITCH_INT_EN,
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PMU_CENTER_PWR_SWITCH_INT_EN,
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PMU_VIO_PWR_SWITCH_INT_EN,
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PMU_GPU_PWR_SWITCH_INT_EN,
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PMU_VCODEC_PWR_SWITCH_INT_EN,
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PMU_VDU_PWR_SWITCH_INT_EN,
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PMU_RGA_PWR_SWITCH_INT_EN,
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PMU_IEP_PWR_SWITCH_INT_EN,
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PMU_VO_PWR_SWITCH_INT_EN,
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PMU_ISP0_PWR_SWITCH_INT_EN = 22,
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PMU_ISP1_PWR_SWITCH_INT_EN,
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PMU_HDCP_PWR_SWITCH_INT_EN,
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PMU_GMAC_PWR_SWITCH_INT_EN,
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PMU_EMMC_PWR_SWITCH_INT_EN,
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PMU_USB3_PWR_SWITCH_INT_EN,
|
|
|
|
PMU_EDP_PWR_SWITCH_INT_EN,
|
|
PMU_GIC_PWR_SWITCH_INT_EN,
|
|
PMU_SD_PWR_SWITCH_INT_EN,
|
|
PMU_SDIOAUDIO_PWR_SWITCH_INT_EN,
|
|
};
|
|
|
|
enum pmu_wkup_status {
|
|
PMU_WKUP_BY_CLSTER_L_INT = 0,
|
|
PMU_WKUP_BY_CLSTER_b_INT,
|
|
PMU_WKUP_BY_GPIO_INT,
|
|
PMU_WKUP_BY_SDIO_DET,
|
|
|
|
PMU_WKUP_BY_SDMMC_DET,
|
|
PMU_WKUP_BY_TIMER = 6,
|
|
PMU_WKUP_BY_USBDEV_DET,
|
|
|
|
PMU_WKUP_BY_M0_SFT,
|
|
PMU_WKUP_BY_M0_WDT_INT,
|
|
PMU_WKUP_BY_TIMEOUT,
|
|
PMU_WKUP_BY_PWM,
|
|
|
|
PMU_WKUP_BY_PCIE = 13,
|
|
};
|
|
|
|
enum pmu_bus_clr {
|
|
PMU_CLR_GPU = 0,
|
|
PMU_CLR_PERILP,
|
|
PMU_CLR_PERIHP,
|
|
PMU_CLR_VCODEC,
|
|
|
|
PMU_CLR_VDU,
|
|
PMU_CLR_RGA,
|
|
PMU_CLR_IEP,
|
|
PMU_CLR_VOPB,
|
|
|
|
PMU_CLR_VOPL,
|
|
PMU_CLR_ISP0,
|
|
PMU_CLR_ISP1,
|
|
PMU_CLR_HDCP,
|
|
|
|
PMU_CLR_USB3,
|
|
PMU_CLR_PERILPM0,
|
|
PMU_CLR_CENTER,
|
|
PMU_CLR_CCIM1,
|
|
|
|
PMU_CLR_CCIM0,
|
|
PMU_CLR_VIO,
|
|
PMU_CLR_MSCH0,
|
|
PMU_CLR_MSCH1,
|
|
|
|
PMU_CLR_ALIVE,
|
|
PMU_CLR_PMU,
|
|
PMU_CLR_EDP,
|
|
PMU_CLR_GMAC,
|
|
|
|
PMU_CLR_EMMC,
|
|
PMU_CLR_CENTER1,
|
|
PMU_CLR_PMUM0,
|
|
PMU_CLR_GIC,
|
|
|
|
PMU_CLR_SD,
|
|
PMU_CLR_SDIOAUDIO,
|
|
};
|
|
|
|
/* PMU bus idle request register */
|
|
enum pmu_bus_idle_req {
|
|
PMU_IDLE_REQ_GPU = 0,
|
|
PMU_IDLE_REQ_PERILP,
|
|
PMU_IDLE_REQ_PERIHP,
|
|
PMU_IDLE_REQ_VCODEC,
|
|
|
|
PMU_IDLE_REQ_VDU,
|
|
PMU_IDLE_REQ_RGA,
|
|
PMU_IDLE_REQ_IEP,
|
|
PMU_IDLE_REQ_VOPB,
|
|
|
|
PMU_IDLE_REQ_VOPL,
|
|
PMU_IDLE_REQ_ISP0,
|
|
PMU_IDLE_REQ_ISP1,
|
|
PMU_IDLE_REQ_HDCP,
|
|
|
|
PMU_IDLE_REQ_USB3,
|
|
PMU_IDLE_REQ_PERILPM0,
|
|
PMU_IDLE_REQ_CENTER,
|
|
PMU_IDLE_REQ_CCIM0,
|
|
|
|
PMU_IDLE_REQ_CCIM1,
|
|
PMU_IDLE_REQ_VIO,
|
|
PMU_IDLE_REQ_MSCH0,
|
|
PMU_IDLE_REQ_MSCH1,
|
|
|
|
PMU_IDLE_REQ_ALIVE,
|
|
PMU_IDLE_REQ_PMU,
|
|
PMU_IDLE_REQ_EDP,
|
|
PMU_IDLE_REQ_GMAC,
|
|
|
|
PMU_IDLE_REQ_EMMC,
|
|
PMU_IDLE_REQ_CENTER1,
|
|
PMU_IDLE_REQ_PMUM0,
|
|
PMU_IDLE_REQ_GIC,
|
|
|
|
PMU_IDLE_REQ_SD,
|
|
PMU_IDLE_REQ_SDIOAUDIO,
|
|
};
|
|
|
|
/* pmu bus idle status register */
|
|
enum pmu_bus_idle_st {
|
|
PMU_IDLE_ST_GPU = 0,
|
|
PMU_IDLE_ST_PERILP,
|
|
PMU_IDLE_ST_PERIHP,
|
|
PMU_IDLE_ST_VCODEC,
|
|
|
|
PMU_IDLE_ST_VDU,
|
|
PMU_IDLE_ST_RGA,
|
|
PMU_IDLE_ST_IEP,
|
|
PMU_IDLE_ST_VOPB,
|
|
|
|
PMU_IDLE_ST_VOPL,
|
|
PMU_IDLE_ST_ISP0,
|
|
PMU_IDLE_ST_ISP1,
|
|
PMU_IDLE_ST_HDCP,
|
|
|
|
PMU_IDLE_ST_USB3,
|
|
PMU_IDLE_ST_PERILPM0,
|
|
PMU_IDLE_ST_CENTER,
|
|
PMU_IDLE_ST_CCIM0,
|
|
|
|
PMU_IDLE_ST_CCIM1,
|
|
PMU_IDLE_ST_VIO,
|
|
PMU_IDLE_ST_MSCH0,
|
|
PMU_IDLE_ST_MSCH1,
|
|
|
|
PMU_IDLE_ST_ALIVE,
|
|
PMU_IDLE_ST_PMU,
|
|
PMU_IDLE_ST_EDP,
|
|
PMU_IDLE_ST_GMAC,
|
|
|
|
PMU_IDLE_ST_EMMC,
|
|
PMU_IDLE_ST_CENTER1,
|
|
PMU_IDLE_ST_PMUM0,
|
|
PMU_IDLE_ST_GIC,
|
|
|
|
PMU_IDLE_ST_SD,
|
|
PMU_IDLE_ST_SDIOAUDIO,
|
|
};
|
|
|
|
enum pmu_bus_idle_ack {
|
|
PMU_IDLE_ACK_GPU = 0,
|
|
PMU_IDLE_ACK_PERILP,
|
|
PMU_IDLE_ACK_PERIHP,
|
|
PMU_IDLE_ACK_VCODEC,
|
|
|
|
PMU_IDLE_ACK_VDU,
|
|
PMU_IDLE_ACK_RGA,
|
|
PMU_IDLE_ACK_IEP,
|
|
PMU_IDLE_ACK_VOPB,
|
|
|
|
PMU_IDLE_ACK_VOPL,
|
|
PMU_IDLE_ACK_ISP0,
|
|
PMU_IDLE_ACK_ISP1,
|
|
PMU_IDLE_ACK_HDCP,
|
|
|
|
PMU_IDLE_ACK_USB3,
|
|
PMU_IDLE_ACK_PERILPM0,
|
|
PMU_IDLE_ACK_CENTER,
|
|
PMU_IDLE_ACK_CCIM0,
|
|
|
|
PMU_IDLE_ACK_CCIM1,
|
|
PMU_IDLE_ACK_VIO,
|
|
PMU_IDLE_ACK_MSCH0,
|
|
PMU_IDLE_ACK_MSCH1,
|
|
|
|
PMU_IDLE_ACK_ALIVE,
|
|
PMU_IDLE_ACK_PMU,
|
|
PMU_IDLE_ACK_EDP,
|
|
PMU_IDLE_ACK_GMAC,
|
|
|
|
PMU_IDLE_ACK_EMMC,
|
|
PMU_IDLE_ACK_CENTER1,
|
|
PMU_IDLE_ACK_PMUM0,
|
|
PMU_IDLE_ACK_GIC,
|
|
|
|
PMU_IDLE_ACK_SD,
|
|
PMU_IDLE_ACK_SDIOAUDIO,
|
|
};
|
|
|
|
enum pmu_cci500_con {
|
|
PMU_PREQ_CCI500_CFG_SW = 0,
|
|
PMU_CLR_PREQ_CCI500_HW,
|
|
PMU_PSTATE_CCI500_0,
|
|
PMU_PSTATE_CCI500_1,
|
|
|
|
PMU_PSTATE_CCI500_2,
|
|
PMU_QREQ_CCI500_CFG_SW,
|
|
PMU_CLR_QREQ_CCI500_HW,
|
|
PMU_QGATING_CCI500_CFG,
|
|
|
|
PMU_PREQ_CCI500_CFG_SW_WMSK = 16,
|
|
PMU_CLR_PREQ_CCI500_HW_WMSK,
|
|
PMU_PSTATE_CCI500_0_WMSK,
|
|
PMU_PSTATE_CCI500_1_WMSK,
|
|
|
|
PMU_PSTATE_CCI500_2_WMSK,
|
|
PMU_QREQ_CCI500_CFG_SW_WMSK,
|
|
PMU_CLR_QREQ_CCI500_HW_WMSK,
|
|
PMU_QGATING_CCI500_CFG_WMSK,
|
|
};
|
|
|
|
enum pmu_adb400_con {
|
|
PMU_PWRDWN_REQ_CXCS_SW = 0,
|
|
PMU_PWRDWN_REQ_CORE_L_SW,
|
|
PMU_PWRDWN_REQ_CORE_L_2GIC_SW,
|
|
PMU_PWRDWN_REQ_GIC2_CORE_L_SW,
|
|
|
|
PMU_PWRDWN_REQ_CORE_B_SW,
|
|
PMU_PWRDWN_REQ_CORE_B_2GIC_SW,
|
|
PMU_PWRDWN_REQ_GIC2_CORE_B_SW,
|
|
|
|
PMU_CLR_CXCS_HW = 8,
|
|
PMU_CLR_CORE_L_HW,
|
|
PMU_CLR_CORE_L_2GIC_HW,
|
|
PMU_CLR_GIC2_CORE_L_HW,
|
|
|
|
PMU_CLR_CORE_B_HW,
|
|
PMU_CLR_CORE_B_2GIC_HW,
|
|
PMU_CLR_GIC2_CORE_B_HW,
|
|
|
|
PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16,
|
|
PMU_PWRDWN_REQ_CORE_L_SW_WMSK,
|
|
PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK,
|
|
PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK,
|
|
|
|
PMU_PWRDWN_REQ_CORE_B_SW_WMSK,
|
|
PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK,
|
|
PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK,
|
|
|
|
PMU_CLR_CXCS_HW_WMSK = 24,
|
|
PMU_CLR_CORE_L_HW_WMSK,
|
|
PMU_CLR_CORE_L_2GIC_HW_WMSK,
|
|
PMU_CLR_GIC2_CORE_L_HW_WMSK,
|
|
|
|
PMU_CLR_CORE_B_HW_WMSK,
|
|
PMU_CLR_CORE_B_2GIC_HW_WMSK,
|
|
PMU_CLR_GIC2_CORE_B_HW_WMSK,
|
|
};
|
|
|
|
enum pmu_adb400_st {
|
|
PMU_PWRDWN_REQ_CXCS_SW_ST = 0,
|
|
PMU_PWRDWN_REQ_CORE_L_SW_ST,
|
|
PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST,
|
|
PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST,
|
|
|
|
PMU_PWRDWN_REQ_CORE_B_SW_ST,
|
|
PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST,
|
|
PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST,
|
|
|
|
PMU_CLR_CXCS_HW_ST = 8,
|
|
PMU_CLR_CORE_L_HW_ST,
|
|
PMU_CLR_CORE_L_2GIC_HW_ST,
|
|
PMU_CLR_GIC2_CORE_L_HW_ST,
|
|
|
|
PMU_CLR_CORE_B_HW_ST,
|
|
PMU_CLR_CORE_B_2GIC_HW_ST,
|
|
PMU_CLR_GIC2_CORE_B_HW_ST,
|
|
};
|
|
|
|
enum pmu_pwrdn_con1 {
|
|
PMU_VD_SCU_L_PWRDN_EN = 0,
|
|
PMU_VD_SCU_B_PWRDN_EN,
|
|
PMU_VD_CENTER_PWRDN_EN,
|
|
};
|
|
|
|
enum pmu_core_pwr_st {
|
|
L2_FLUSHDONE_CLUSTER_L = 0,
|
|
STANDBY_BY_WFIL2_CLUSTER_L,
|
|
|
|
L2_FLUSHDONE_CLUSTER_B = 10,
|
|
STANDBY_BY_WFIL2_CLUSTER_B,
|
|
};
|
|
|
|
#define PMU_WKUP_CFG0 0x00
|
|
#define PMU_WKUP_CFG1 0x04
|
|
#define PMU_WKUP_CFG2 0x08
|
|
#define PMU_WKUP_CFG3 0x0c
|
|
#define PMU_WKUP_CFG4 0x10
|
|
#define PMU_PWRDN_CON 0x14
|
|
#define PMU_PWRDN_ST 0x18
|
|
#define PMU_PLL_CON 0x1c
|
|
#define PMU_PWRMODE_CON 0x20
|
|
#define PMU_SFT_CON 0x24
|
|
#define PMU_INT_CON 0x28
|
|
#define PMU_INT_ST 0x2c
|
|
#define PMU_GPIO0_POS_INT_CON 0x30
|
|
#define PMU_GPIO0_NEG_INT_CON 0x34
|
|
#define PMU_GPIO1_POS_INT_CON 0x38
|
|
#define PMU_GPIO1_NEG_INT_CON 0x3c
|
|
#define PMU_GPIO0_POS_INT_ST 0x40
|
|
#define PMU_GPIO0_NEG_INT_ST 0x44
|
|
#define PMU_GPIO1_POS_INT_ST 0x48
|
|
#define PMU_GPIO1_NEG_INT_ST 0x4c
|
|
#define PMU_PWRDN_INTEN 0x50
|
|
#define PMU_PWRDN_STATUS 0x54
|
|
#define PMU_WAKEUP_STATUS 0x58
|
|
#define PMU_BUS_CLR 0x5c
|
|
#define PMU_BUS_IDLE_REQ 0x60
|
|
#define PMU_BUS_IDLE_ST 0x64
|
|
#define PMU_BUS_IDLE_ACK 0x68
|
|
#define PMU_CCI500_CON 0x6c
|
|
#define PMU_ADB400_CON 0x70
|
|
#define PMU_ADB400_ST 0x74
|
|
#define PMU_POWER_ST 0x78
|
|
#define PMU_CORE_PWR_ST 0x7c
|
|
#define PMU_OSC_CNT 0x80
|
|
#define PMU_PLLLOCK_CNT 0x84
|
|
#define PMU_PLLRST_CNT 0x88
|
|
#define PMU_STABLE_CNT 0x8c
|
|
#define PMU_DDRIO_PWRON_CNT 0x90
|
|
#define PMU_WAKEUP_RST_CLR_CNT 0x94
|
|
#define PMU_DDR_SREF_ST 0x98
|
|
#define PMU_SCU_L_PWRDN_CNT 0x9c
|
|
#define PMU_SCU_L_PWRUP_CNT 0xa0
|
|
#define PMU_SCU_B_PWRDN_CNT 0xa4
|
|
#define PMU_SCU_B_PWRUP_CNT 0xa8
|
|
#define PMU_GPU_PWRDN_CNT 0xac
|
|
#define PMU_GPU_PWRUP_CNT 0xb0
|
|
#define PMU_CENTER_PWRDN_CNT 0xb4
|
|
#define PMU_CENTER_PWRUP_CNT 0xb8
|
|
#define PMU_TIMEOUT_CNT 0xbc
|
|
#define PMU_CPU0APM_CON 0xc0
|
|
#define PMU_CPU1APM_CON 0xc4
|
|
#define PMU_CPU2APM_CON 0xc8
|
|
#define PMU_CPU3APM_CON 0xcc
|
|
#define PMU_CPU0BPM_CON 0xd0
|
|
#define PMU_CPU1BPM_CON 0xd4
|
|
#define PMU_NOC_AUTO_ENA 0xd8
|
|
#define PMU_PWRDN_CON1 0xdc
|
|
|
|
#define PMUGRF_GPIO1A_IOMUX 0x10
|
|
#define AP_PWROFF 0x0a
|
|
#define GPIO1A6_IOMUX BITS_WITH_WMASK(0, 3, 12)
|
|
#define TSADC_INT_PIN 38
|
|
#define CORES_PM_DISABLE 0x0
|
|
|
|
#define PD_CTR_LOOP 500
|
|
#define CHK_CPU_LOOP 500
|
|
#define MAX_WAIT_CONUT 1000
|
|
|
|
#endif /* __PMU_H__ */
|