265 lines
8.7 KiB
C
265 lines
8.7 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl31.h>
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#include <bl_common.h>
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#include <console.h>
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#include <cortex_a57.h>
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#include <cortex_a53.h>
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#include <debug.h>
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#include <errno.h>
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#include <memctrl.h>
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <stddef.h>
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#include <tegra_private.h>
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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* of trusted SRAM
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******************************************************************************/
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extern unsigned long __RO_START__;
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extern unsigned long __RO_END__;
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extern unsigned long __BL31_END__;
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#if USE_COHERENT_MEM
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extern unsigned long __COHERENT_RAM_START__;
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extern unsigned long __COHERENT_RAM_END__;
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#endif
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extern uint64_t tegra_bl31_phys_base;
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/*
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* The next 3 constants identify the extents of the code, RO data region and the
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* limit of the BL3-1 image. These addresses are used by the MMU setup code and
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* therefore they must be page-aligned. It is the responsibility of the linker
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* script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
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* refer to page-aligned addresses.
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*/
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#define BL31_RO_BASE (unsigned long)(&__RO_START__)
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#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
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#define BL31_END (unsigned long)(&__BL31_END__)
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#if USE_COHERENT_MEM
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
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* refer to page-aligned addresses.
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*/
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#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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#endif
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static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
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static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
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.tzdram_size = (uint64_t)TZDRAM_SIZE
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};
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/*******************************************************************************
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* This variable holds the non-secure image entry address
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******************************************************************************/
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extern uint64_t ns_image_entrypoint;
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type.
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******************************************************************************/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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if (type == NON_SECURE)
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return &bl33_image_ep_info;
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if (type == SECURE)
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return &bl32_image_ep_info;
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return NULL;
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}
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/*******************************************************************************
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* Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
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* passes this platform specific information.
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******************************************************************************/
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plat_params_from_bl2_t *bl31_get_plat_params(void)
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{
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return &plat_bl31_params_from_bl2;
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}
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/*******************************************************************************
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* Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
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* info.
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******************************************************************************/
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void bl31_early_platform_setup(bl31_params_t *from_bl2,
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void *plat_params_from_bl2)
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{
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plat_params_from_bl2_t *plat_params =
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(plat_params_from_bl2_t *)plat_params_from_bl2;
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/*
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* Configure the UART port to be used as the console
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*/
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console_init(TEGRA_BOOT_UART_BASE, TEGRA_BOOT_UART_CLK_IN_HZ,
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TEGRA_CONSOLE_BAUDRATE);
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/* Initialise crash console */
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plat_crash_console_init();
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/*
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* Copy BL3-3, BL3-2 entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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bl33_image_ep_info = *from_bl2->bl33_ep_info;
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bl32_image_ep_info = *from_bl2->bl32_ep_info;
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/*
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* Parse platform specific parameters - TZDRAM aperture size
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*/
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if (plat_params)
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plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
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}
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/*******************************************************************************
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* Initialize the gic, configure the SCR.
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******************************************************************************/
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void bl31_platform_setup(void)
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{
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uint32_t tmp_reg;
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/*
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* Initialize delay timer
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*/
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tegra_delay_timer_init();
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/*
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* Setup secondary CPU POR infrastructure.
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*/
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plat_secondary_setup();
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/*
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* Initial Memory Controller configuration.
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*/
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tegra_memctrl_setup();
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/*
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* Do initial security configuration to allow DRAM/device access.
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*/
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tegra_memctrl_tzdram_setup(tegra_bl31_phys_base,
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plat_bl31_params_from_bl2.tzdram_size);
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/* Set the next EL to be AArch64 */
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tmp_reg = SCR_RES1_BITS | SCR_RW_BIT;
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write_scr(tmp_reg);
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/* Initialize the gic cpu and distributor interfaces */
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tegra_gic_setup();
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this only intializes the mmu in a quick and dirty way.
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******************************************************************************/
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void bl31_plat_arch_setup(void)
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{
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unsigned long bl31_base_pa = tegra_bl31_phys_base;
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unsigned long total_base = bl31_base_pa;
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unsigned long total_size = BL32_BASE - BL31_RO_BASE;
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unsigned long ro_start = bl31_base_pa;
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unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE;
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const mmap_region_t *plat_mmio_map = NULL;
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#if USE_COHERENT_MEM
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unsigned long coh_start, coh_size;
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#endif
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/* add memory regions */
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mmap_add_region(total_base, total_base,
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total_size,
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MT_MEMORY | MT_RW | MT_SECURE);
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mmap_add_region(ro_start, ro_start,
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ro_size,
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MT_MEMORY | MT_RO | MT_SECURE);
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#if USE_COHERENT_MEM
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coh_start = total_base + (BL31_COHERENT_RAM_BASE - BL31_RO_BASE);
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coh_size = BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE;
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mmap_add_region(coh_start, coh_start,
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coh_size,
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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/* add MMIO space */
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plat_mmio_map = plat_get_mmio_map();
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if (plat_mmio_map)
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mmap_add(plat_mmio_map);
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else
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WARN("MMIO map not available\n");
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/* set up translation tables */
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init_xlat_tables();
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/* enable the MMU */
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enable_mmu_el3(0);
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}
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/*******************************************************************************
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* Check if the given NS DRAM range is valid
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******************************************************************************/
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int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
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{
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uint64_t end = base + size_in_bytes - 1;
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/*
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* Check if the NS DRAM address is valid
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*/
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if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) ||
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(base >= end)) {
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ERROR("NS address is out-of-bounds!\n");
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return -EFAULT;
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}
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/*
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* TZDRAM aperture contains the BL31 and BL32 images, so we need
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* to check if the NS DRAM range overlaps the TZDRAM aperture.
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*/
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if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) {
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ERROR("NS address overlaps TZDRAM!\n");
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return -ENOTSUP;
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}
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/* valid NS address */
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return 0;
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}
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