270 lines
5.5 KiB
C
270 lines
5.5 KiB
C
/*
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* Copyright (c) 2020, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <string.h>
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#include <drivers/delay_timer.h>
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#include <mt_cpu_pm_cpc.h>
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#include <mt_timer.h>
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struct mtk_cpc_dev {
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int auto_off;
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unsigned int auto_thres_tick;
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};
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static struct mtk_cpc_dev cpc;
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static int mtk_cpc_last_core_prot(uint32_t prot_req,
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uint32_t resp_reg, uint32_t resp_ofs)
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{
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uint32_t sta, retry;
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retry = 0U;
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while (retry++ < RETRY_CNT_MAX) {
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mmio_write_32(CPC_MCUSYS_LAST_CORE_REQ, prot_req);
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udelay(1U);
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sta = (mmio_read_32(resp_reg) >> resp_ofs) & CPC_PROT_RESP_MASK;
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if (sta == PROT_SUCCESS) {
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return CPC_SUCCESS;
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} else if (sta == PROT_GIVEUP) {
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return CPC_ERR_FAIL;
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}
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}
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return CPC_ERR_TIMEOUT;
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}
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int mtk_cpu_pm_mcusys_prot_aquire(void)
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{
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return mtk_cpc_last_core_prot(
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MCUSYS_PROT_SET,
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CPC_MCUSYS_LAST_CORE_RESP,
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MCUSYS_RESP_OFS);
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}
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void mtk_cpu_pm_mcusys_prot_release(void)
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{
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mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR);
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}
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int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster)
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{
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return mtk_cpc_last_core_prot(
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CPUSYS_PROT_SET,
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CPC_MCUSYS_MP_LAST_CORE_RESP,
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CPUSYS_RESP_OFS);
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}
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void mtk_cpu_pm_cluster_prot_release(unsigned int cluster)
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{
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mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR);
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}
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static void mtk_cpc_cluster_cnt_backup(void)
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{
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uint32_t backup_cnt;
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uint32_t curr_cnt;
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uint32_t cnt_mask = GENMASK(14, 0);
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uint32_t clr_mask = GENMASK(1, 0);
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/* Single Cluster */
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backup_cnt = mmio_read_32(CPC_CLUSTER_CNT_BACKUP);
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curr_cnt = mmio_read_32(CPC_MCUSYS_CLUSTER_COUNTER);
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/* Get off count if dormant count is 0 */
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if ((curr_cnt & cnt_mask) == 0U) {
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curr_cnt = (curr_cnt >> 16) & cnt_mask;
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} else {
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curr_cnt = curr_cnt & cnt_mask;
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}
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mmio_write_32(CPC_CLUSTER_CNT_BACKUP, backup_cnt + curr_cnt);
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mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, clr_mask);
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}
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static inline void mtk_cpc_mcusys_off_en(void)
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{
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mmio_write_32(CPC_MCUSYS_PWR_CTRL, 1U);
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}
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static inline void mtk_cpc_mcusys_off_dis(void)
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{
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mmio_write_32(CPC_MCUSYS_PWR_CTRL, 0U);
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}
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void mtk_cpc_mcusys_off_reflect(void)
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{
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mtk_cpc_mcusys_off_dis();
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mtk_cpu_pm_mcusys_prot_release();
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}
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int mtk_cpc_mcusys_off_prepare(void)
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{
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if (mtk_cpu_pm_mcusys_prot_aquire() != CPC_SUCCESS) {
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return CPC_ERR_FAIL;
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}
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mtk_cpc_cluster_cnt_backup();
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mtk_cpc_mcusys_off_en();
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return CPC_SUCCESS;
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}
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void mtk_cpc_core_on_hint_set(unsigned int cpu)
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{
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mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_SET, BIT(cpu));
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}
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void mtk_cpc_core_on_hint_clr(unsigned int cpu)
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{
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mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_CLR, BIT(cpu));
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}
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static void mtk_cpc_dump_timestamp(void)
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{
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uint32_t id;
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for (id = 0U; id < CPC_TRACE_ID_NUM; id++) {
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mmio_write_32(CPC_MCUSYS_TRACE_SEL, id);
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memcpy((void *)(uintptr_t)CPC_TRACE_SRAM(id),
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(const void *)(uintptr_t)CPC_MCUSYS_TRACE_DATA,
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CPC_TRACE_SIZE);
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}
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}
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void mtk_cpc_time_sync(void)
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{
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uint64_t kt;
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uint32_t systime_l, systime_h;
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kt = sched_clock();
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systime_l = mmio_read_32(CNTSYS_L_REG);
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systime_h = mmio_read_32(CNTSYS_H_REG);
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/* sync kernel timer to cpc */
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mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE, (uint32_t)kt);
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mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE, (uint32_t)(kt >> 32));
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/* sync system timer to cpc */
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mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE, systime_l);
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mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE, systime_h);
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}
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static void mtk_cpc_config(uint32_t cfg, uint32_t data)
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{
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uint32_t val;
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uint32_t reg = 0U;
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switch (cfg) {
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case CPC_SMC_CONFIG_PROF:
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reg = CPC_MCUSYS_CPC_DBG_SETTING;
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val = mmio_read_32(reg);
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val = (data != 0U) ? (val | CPC_PROF_EN) : (val & ~CPC_PROF_EN);
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break;
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case CPC_SMC_CONFIG_AUTO_OFF:
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reg = CPC_MCUSYS_CPC_FLOW_CTRL_CFG;
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val = mmio_read_32(reg);
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if (data != 0U) {
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val |= CPC_AUTO_OFF_EN;
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cpc.auto_off = 1;
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} else {
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val &= ~CPC_AUTO_OFF_EN;
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cpc.auto_off = 0;
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}
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break;
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case CPC_SMC_CONFIG_AUTO_OFF_THRES:
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reg = CPC_MCUSYS_CPC_OFF_THRES;
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cpc.auto_thres_tick = us_to_ticks(data);
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val = cpc.auto_thres_tick;
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break;
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case CPC_SMC_CONFIG_CNT_CLR:
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reg = CPC_MCUSYS_CLUSTER_COUNTER_CLR;
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val = GENMASK(1, 0); /* clr_mask */
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break;
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case CPC_SMC_CONFIG_TIME_SYNC:
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mtk_cpc_time_sync();
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break;
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default:
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break;
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}
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if (reg != 0U) {
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mmio_write_32(reg, val);
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}
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}
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static uint32_t mtk_cpc_read_config(uint32_t cfg)
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{
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uint32_t res = 0U;
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switch (cfg) {
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case CPC_SMC_CONFIG_PROF:
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res = (mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN) ?
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1U : 0U;
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break;
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case CPC_SMC_CONFIG_AUTO_OFF:
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res = cpc.auto_off;
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break;
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case CPC_SMC_CONFIG_AUTO_OFF_THRES:
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res = ticks_to_us(cpc.auto_thres_tick);
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break;
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case CPC_SMC_CONFIG_CNT_CLR:
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break;
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default:
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break;
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}
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return res;
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}
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uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2)
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{
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uint64_t res = 0ULL;
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switch (act) {
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case CPC_SMC_EVENT_DUMP_TRACE_DATA:
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mtk_cpc_dump_timestamp();
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break;
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case CPC_SMC_EVENT_GIC_DPG_SET:
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/* isolated_status = x2; */
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break;
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case CPC_SMC_EVENT_CPC_CONFIG:
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mtk_cpc_config((uint32_t)arg1, (uint32_t)arg2);
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break;
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case CPC_SMC_EVENT_READ_CONFIG:
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res = mtk_cpc_read_config((uint32_t)arg1);
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break;
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default:
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break;
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}
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return res;
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}
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void mtk_cpc_init(void)
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{
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mmio_write_32(CPC_MCUSYS_CPC_DBG_SETTING,
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mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING)
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| CPC_DBG_EN
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| CPC_CALC_EN);
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cpc.auto_off = 1;
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cpc.auto_thres_tick = us_to_ticks(8000);
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mmio_write_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG,
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mmio_read_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG)
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| CPC_OFF_PRE_EN
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| (cpc.auto_off ? CPC_AUTO_OFF_EN : 0U));
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mmio_write_32(CPC_MCUSYS_CPC_OFF_THRES, cpc.auto_thres_tick);
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}
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