147 lines
3.2 KiB
C
147 lines
3.2 KiB
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/gicv3.h>
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#include <bl31/interrupt_mgmt.h>
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#include <../drivers/arm/gic/v3/gicv3_private.h>
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#include <mt_gic_v3.h>
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#include <mtk_plat_common.h>
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#include "plat_private.h"
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <stdint.h>
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#include <stdio.h>
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#define NR_INT_POL_CTL 20
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uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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/*
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* We save and restore the GICv3 context on system suspend. Allocate the
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* data in the designated EL3 Secure carve-out memory
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*/
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gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram");
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gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram");
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static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
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{
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return plat_core_pos_by_mpidr(mpidr);
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}
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gicv3_driver_data_t mt_gicv3_data = {
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.gicd_base = MT_GIC_BASE,
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.gicr_base = MT_GIC_RDIST_BASE,
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = rdistif_base_addrs,
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.mpidr_to_core_pos = mt_mpidr_to_core_pos,
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};
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void setup_int_schedule_mode(enum irq_schedule_mode mode,
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unsigned int active_cpu)
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{
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assert(mode <= HW_MODE);
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assert(active_cpu <= 0xFF);
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if (mode == HW_MODE) {
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mmio_write_32(GIC_INT_MASK,
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(mmio_read_32(GIC_INT_MASK) & ~(GIC500_ACTIVE_SEL_MASK))
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| (0x1 << GIC500_ACTIVE_SEL_SHIFT));
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} else if (mode == SW_MODE) {
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mmio_write_32(GIC_INT_MASK,
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(mmio_read_32(GIC_INT_MASK) & ~(GIC500_ACTIVE_SEL_MASK)));
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}
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mmio_write_32(GIC_INT_MASK,
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(mmio_read_32(GIC_INT_MASK) & ~(GIC500_ACTIVE_CPU_MASK))
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| (active_cpu << GIC500_ACTIVE_CPU_SHIFT));
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return;
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}
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void clear_sec_pol_ctl_en(void)
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{
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unsigned int i;
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/* total 19 polarity ctrl registers */
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for (i = 0; i <= NR_INT_POL_CTL - 1; i++) {
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mmio_write_32((SEC_POL_CTL_EN0 + (i * 4)), 0);
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}
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dsb();
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}
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void mt_gic_driver_init(void)
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{
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gicv3_driver_init(&mt_gicv3_data);
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}
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void mt_gic_init(void)
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{
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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setup_int_schedule_mode(SW_MODE, 0xf);
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clear_sec_pol_ctl_en();
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}
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void mt_gic_set_pending(uint32_t irq)
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{
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gicv3_set_interrupt_pending(irq, plat_my_core_pos());
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}
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uint32_t mt_gic_get_pending(uint32_t irq)
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{
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uint32_t bit = 1 << (irq % 32);
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return (mmio_read_32(gicv3_driver_data->gicd_base +
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GICD_ISPENDR + irq / 32 * 4) & bit) ? 1 : 0;
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}
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void mt_gic_cpuif_enable(void)
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{
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void mt_gic_cpuif_disable(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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}
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void mt_gic_pcpu_init(void)
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{
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gicv3_rdistif_init(plat_my_core_pos());
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}
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void mt_gic_irq_save(void)
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{
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gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx);
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gicv3_distif_save(&dist_ctx);
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}
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void mt_gic_irq_restore(void)
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{
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gicv3_distif_init_restore(&dist_ctx);
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gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx);
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}
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void mt_gic_sync_dcm_enable(void)
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{
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unsigned int val = mmio_read_32(GIC_SYNC_DCM);
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val &= ~GIC_SYNC_DCM_MASK;
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mmio_write_32(GIC_SYNC_DCM, val | GIC_SYNC_DCM_ON);
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}
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void mt_gic_sync_dcm_disable(void)
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{
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unsigned int val = mmio_read_32(GIC_SYNC_DCM);
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val &= ~GIC_SYNC_DCM_MASK;
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mmio_write_32(GIC_SYNC_DCM, val | GIC_SYNC_DCM_OFF);
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}
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