Sieu Mun Tang f571183b06 fix(intel): make FPGA memory configurations platform specific ... Define FPGA_CONFIG_SIZE and FPGA_CONFIG_ADDR in platform-specific header. This is due to different allocated sizes between platforms. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: Iac4fbf4d4940cdf31834a9d4332f9292870dee76		2022-03-09 09:14:21 +08:00
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agilex_clock_manager.h	plat: intel: set DRVSEL and SMPLSEL for DWMMC	2020-06-08 22:03:34 +00:00
agilex_memory_controller.h	intel: Enable bridge access in Intel platform	2020-01-16 10:53:21 +08:00
agilex_mmc.h	plat: intel: set DRVSEL and SMPLSEL for DWMMC	2020-06-08 22:03:34 +00:00
agilex_noc.h	intel: Adds support for Agilex platform	2019-07-17 19:06:49 +08:00
agilex_pinmux.h	intel: Refactor common platform code [1/5]	2019-11-28 12:47:57 +08:00
socfpga_plat_def.h	fix(intel): make FPGA memory configurations platform specific	2022-03-09 09:14:21 +08:00