159 lines
4.1 KiB
C
159 lines
4.1 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/mentor/mi2cv.h>
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#include <lib/mmio.h>
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#include <mv_ddr_if.h>
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#include <mvebu_def.h>
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#include <plat_marvell.h>
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#define MVEBU_CP_MPP_CTRL37_OFFS 20
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#define MVEBU_CP_MPP_CTRL38_OFFS 24
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#define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA 0x2
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#define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA 0x2
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#define MVEBU_MPP_CTRL_MASK 0xf
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/*
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* This struct provides the DRAM training code with
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* the appropriate board DRAM configuration
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*/
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struct mv_ddr_iface dram_iface_ap0 = {
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.ap_base = MVEBU_REGS_BASE_AP(0),
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.state = MV_DDR_IFACE_NRDY,
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.validation = MV_DDR_MEMORY_CHECK,
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.sscg = SSCG_EN,
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.id = 0,
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.iface_base_addr = 0,
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.tm = {
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
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{ { { {0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0},
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{0x1, 0x0, 0, 0} },
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SPEED_BIN_DDR_2400T, /* speed_bin */
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MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
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MV_DDR_DIE_CAP_8GBIT, /* die capacity */
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MV_DDR_FREQ_SAR, /* frequency */
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0, 0, /* cas_l, cas_wl */
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MV_DDR_TEMP_LOW} }, /* temperature */
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#if DDR32
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MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
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#else
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MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
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#endif
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MV_DDR_CFG_SPD, /* ddr configuration data src */
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NOT_COMBINED, /* ddr twin-die combined*/
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{ {0} }, /* raw spd data */
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{0}, /* timing parameters */
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{ /* electrical configuration */
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{ /* memory electrical configuration */
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MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
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{ /* rtt_park 1cs */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV4,
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/* rtt_park 2cs */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV1
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},
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{ /* rtt_wr 1cs */
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MV_DDR_RTT_WR_DYN_ODT_OFF,
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/* rtt_wr 2cs */
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MV_DDR_RTT_WR_RZQ_DIV2
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},
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MV_DDR_DIC_RZQ_DIV7 /* dic */
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},
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{ /* phy electrical configuration */
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MV_DDR_OHM_30, /* data_drv_p */
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MV_DDR_OHM_30, /* data_drv_n */
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MV_DDR_OHM_30, /* ctrl_drv_p */
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MV_DDR_OHM_30, /* ctrl_drv_n */
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{
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MV_DDR_OHM_60, /* odt_p 1cs */
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MV_DDR_OHM_120 /* odt_p 2cs */
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},
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{
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MV_DDR_OHM_60, /* odt_n 1cs */
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MV_DDR_OHM_120 /* odt_n 2cs */
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},
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},
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{ /* mac electrical configuration */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
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MV_DDR_ODT_CFG_ALWAYS_ON,/* odtcfg_write */
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MV_DDR_ODT_CFG_NORMAL /* odtcfg_read */
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},
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},
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},
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};
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/* Pointer to the first DRAM interface in the system */
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struct mv_ddr_iface *ptr_iface = &dram_iface_ap0;
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struct mv_ddr_iface *mv_ddr_iface_get(void)
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{
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/* Return current ddr interface */
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return ptr_iface;
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}
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struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
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{
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/* Return the board topology as defined in the board code */
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return &ptr_iface->tm;
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}
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static void mpp_config(void)
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{
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uintptr_t reg;
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uint32_t val;
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reg = MVEBU_CP_MPP_REGS(0, 4);
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/* configure CP0 MPP 37 and 38 to i2c */
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val = mmio_read_32(reg);
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val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) |
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(MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS));
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val |= (MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA <<
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MVEBU_CP_MPP_CTRL37_OFFS) |
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(MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA <<
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MVEBU_CP_MPP_CTRL38_OFFS);
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mmio_write_32(reg, val);
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}
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/*
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* This function may modify the default DRAM parameters
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* based on information received from SPD or bootloader
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* configuration located on non volatile storage
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*/
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void plat_marvell_dram_update_topology(void)
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{
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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INFO("Gathering DRAM information\n");
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if (tm->cfg_src == MV_DDR_CFG_SPD) {
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/* configure MPPs to enable i2c */
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mpp_config();
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/* initialize i2c */
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i2c_init((void *)MVEBU_CP0_I2C_BASE);
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/* select SPD memory page 0 to access DRAM configuration */
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i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 0);
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/* read data from spd */
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i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
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sizeof(tm->spd_data.all_bytes));
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}
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}
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