193 lines
4.8 KiB
C
193 lines
4.8 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <armada_common.h>
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#include <mvebu_def.h>
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/*
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* If bootrom is currently at BLE there's no need to include the memory
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* maps structure at this point
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*/
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* AMB Configuration
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*****************************************************************************
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*/
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struct addr_map_win amb_memory_map_cp0[] = {
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/* CP0 SPI1 CS0 Direct Mode access */
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{0xe800, 0x2000000, AMB_SPI1_CS0_ID},
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};
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int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
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uintptr_t base)
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{
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switch (base) {
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case MVEBU_CP_REGS_BASE(0):
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*win = amb_memory_map_cp0;
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*size = ARRAY_SIZE(amb_memory_map_cp0);
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return 0;
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case MVEBU_CP_REGS_BASE(1):
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case MVEBU_CP_REGS_BASE(2):
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default:
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*size = 0;
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*win = 0;
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return 1;
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}
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}
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#endif
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/*****************************************************************************
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* IO WIN Configuration
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*****************************************************************************
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*/
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struct addr_map_win io_win_memory_map[] = {
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#if (CP_COUNT > 1)
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/* SB (MCi0) internal regs */
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{0x00000000f4000000, 0x2000000, MCI_0_TID},
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#if (CP_COUNT > 2)
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/* SB (MCi1) internal regs */
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{0x00000000f6000000, 0x2000000, MCI_1_TID},
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#endif
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#endif
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#ifndef IMAGE_BLE
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/* SB (MCi0) PCIe0-2 on CP1 */
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{0x00000000e2000000, 0x3000000, MCI_0_TID},
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/* SB (MCi1) PCIe0-2 on CP2 */
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{0x00000000e5000000, 0x3000000, MCI_1_TID},
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/* MCI 0 indirect window */
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{MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
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/* MCI 1 indirect window */
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{MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
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#endif
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};
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/* Global Control Register - window default target */
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uint32_t marvell_get_io_win_gcr_target(int ap_index)
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{
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/*
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* PIDI == iMCIP AP to SB internal MoChi connection.
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* In other words CP0
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*/
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return PIDI_TID;
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}
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int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
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uint32_t *size)
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{
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*win = io_win_memory_map;
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if (*win == NULL)
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*size = 0;
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else
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*size = ARRAY_SIZE(io_win_memory_map);
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return 0;
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}
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* IOB Configuration
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*****************************************************************************
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*/
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struct addr_map_win iob_memory_map_cp0[] = {
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/* SPI1_CS0 (RUNIT) window */
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{0x00000000e8000000, 0x2000000, RUNIT_TID},
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/* PEX2_X1 window */
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{0x00000000e1000000, 0x1000000, PEX2_TID},
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/* PEX1_X1 window */
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{0x00000000e0000000, 0x1000000, PEX1_TID},
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/* PEX0_X4 window */
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{0x00000000c0000000, 0x20000000, PEX0_TID},
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};
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struct addr_map_win iob_memory_map_cp1[] = {
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/* PEX2_X1 window */
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{0x00000000e4000000, 0x1000000, PEX2_TID},
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/* PEX1_X1 window */
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{0x00000000e3000000, 0x1000000, PEX1_TID},
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/* PEX0_X4 window */
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{0x00000000e2000000, 0x1000000, PEX0_TID},
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};
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struct addr_map_win iob_memory_map_cp2[] = {
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/* PEX2_X1 window */
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{0x00000000e7000000, 0x1000000, PEX2_TID},
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/* PEX1_X1 window */
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{0x00000000e6000000, 0x1000000, PEX1_TID},
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/* PEX0_X4 window */
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{0x00000000e5000000, 0x1000000, PEX0_TID},
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};
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int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
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uintptr_t base)
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{
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switch (base) {
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case MVEBU_CP_REGS_BASE(0):
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*win = iob_memory_map_cp0;
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*size = ARRAY_SIZE(iob_memory_map_cp0);
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return 0;
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case MVEBU_CP_REGS_BASE(1):
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*win = iob_memory_map_cp1;
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*size = ARRAY_SIZE(iob_memory_map_cp1);
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return 0;
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case MVEBU_CP_REGS_BASE(2):
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*win = iob_memory_map_cp2;
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*size = ARRAY_SIZE(iob_memory_map_cp2);
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return 0;
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default:
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*size = 0;
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*win = 0;
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return 1;
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}
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}
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#endif
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/*****************************************************************************
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* CCU Configuration
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*****************************************************************************
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*/
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struct addr_map_win ccu_memory_map[] = { /* IO window */
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#ifdef IMAGE_BLE
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{0x00000000f2000000, 0x6000000, IO_0_TID}, /* IO window */
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#else
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#if LLC_SRAM
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{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
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#endif
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{0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
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{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
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{0x0000002000000000, 0x70e000000, IO_0_TID}, /* IO for CV-OS */
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#endif
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};
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uint32_t marvell_get_ccu_gcr_target(int ap)
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{
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return DRAM_0_TID;
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}
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int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win,
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uint32_t *size)
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{
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*win = ccu_memory_map;
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*size = ARRAY_SIZE(ccu_memory_map);
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return 0;
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}
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#ifdef IMAGE_BLE
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/*****************************************************************************
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* SKIP IMAGE Configuration
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*****************************************************************************
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*/
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void *plat_get_skip_image_data(void)
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{
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/* No recovery button on CN-9130 board? */
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return NULL;
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}
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#endif
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