Jeenu Viswambharan 385f1dbb29 GIC: Fix Group 0 enabling ... At present, the GIC drivers enable Group 0 interrupts only if there are Secure SPIs listed in the interrupt properties/list. This means that, even if there are Group 0 SGIs/PPIs configured, the group remained disabled in the absence of a Group 0 SPI. Modify both GICv2 and GICv3 SGI/PPI configuration to enable Group 0 when corresponding SGIs/PPIs are present. Change-Id: Id123e8aaee0c22b476eebe3800340906d83bbc6d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>		2017-11-13 07:49:30 +00:00
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arm_gicv3_common.c	GICv3: add functions for save and restore	2017-10-05 16:47:53 +01:00
gic500.c	GICv3: add functions for save and restore	2017-10-05 16:47:53 +01:00
gic600.c	GICv3: add functions for save and restore	2017-10-05 16:47:53 +01:00
gicv3_helpers.c	GIC: Fix Group 0 enabling	2017-11-13 07:49:30 +00:00
gicv3_main.c	GIC: Fix Group 0 enabling	2017-11-13 07:49:30 +00:00
gicv3_private.h	GIC: Fix Group 0 enabling	2017-11-13 07:49:30 +00:00