214 lines
7.6 KiB
C
214 lines
7.6 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <cci400.h>
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#include <console.h>
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#include <debug.h>
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include "../../bl1/bl1_private.h"
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#include "juno_def.h"
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#include "juno_private.h"
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#if USE_COHERENT_MEM
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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* of trusted RAM
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******************************************************************************/
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extern unsigned long __COHERENT_RAM_START__;
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extern unsigned long __COHERENT_RAM_END__;
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
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* page-aligned addresses.
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*/
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#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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#endif
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/* Data structure which holds the extents of the trusted RAM for BL1 */
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static meminfo_t bl1_tzram_layout;
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meminfo_t *bl1_plat_sec_mem_layout(void)
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{
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return &bl1_tzram_layout;
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}
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/*******************************************************************************
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* Perform any BL1 specific platform actions.
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******************************************************************************/
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void bl1_early_platform_setup(void)
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{
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const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
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/* Initialize the console to provide early debug support */
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console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE);
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/*
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* Enable CCI-400 for this cluster. No need for locks as no other cpu is
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* active at the moment
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*/
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cci_init(CCI400_BASE,
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CCI400_SL_IFACE3_CLUSTER_IX,
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CCI400_SL_IFACE4_CLUSTER_IX);
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cci_enable_cluster_coherency(read_mpidr());
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/* Allow BL1 to see the whole Trusted RAM */
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bl1_tzram_layout.total_base = TZRAM_BASE;
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bl1_tzram_layout.total_size = TZRAM_SIZE;
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/* Calculate how much RAM BL1 is using and how much remains free */
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bl1_tzram_layout.free_base = TZRAM_BASE;
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bl1_tzram_layout.free_size = TZRAM_SIZE;
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reserve_mem(&bl1_tzram_layout.free_base,
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&bl1_tzram_layout.free_size,
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BL1_RAM_BASE,
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bl1_size);
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INFO("BL1: 0x%lx - 0x%lx [size = %u]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
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bl1_size);
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}
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/*
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* Address of slave 'n' security setting in the NIC-400 address region
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* control
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* TODO: Ideally this macro should be moved in a "nic-400.h" header file but
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* it would be the only thing in there so it's not worth it at the moment.
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*/
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#define NIC400_ADDR_CTRL_SECURITY_REG(n) (0x8 + (n) * 4)
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static void init_nic400(void)
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{
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/*
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* NIC-400 Access Control Initialization
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*
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* Define access privileges by setting each corresponding bit to:
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* 0 = Secure access only
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* 1 = Non-secure access allowed
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*/
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/*
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* Allow non-secure access to some SOC regions, excluding UART1, which
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* remains secure.
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* Note: This is the NIC-400 device on the SOC
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*/
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mmio_write_32(SOC_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_EHCI), ~0);
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mmio_write_32(SOC_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_TLX_MASTER), ~0);
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mmio_write_32(SOC_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_OHCI), ~0);
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mmio_write_32(SOC_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_PL354_SMC), ~0);
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mmio_write_32(SOC_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_APB4_BRIDGE), ~0);
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mmio_write_32(SOC_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_BOOTSEC_BRIDGE),
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~SOC_NIC400_BOOTSEC_BRIDGE_UART1);
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/*
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* Allow non-secure access to some CSS regions.
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* Note: This is the NIC-400 device on the CSS
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*/
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mmio_write_32(CSS_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE),
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~0);
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}
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#define PCIE_SECURE_REG 0x3000
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#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) /* REG and MEM access bits */
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static void init_pcie(void)
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{
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/*
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* PCIE Root Complex Security settings to enable non-secure
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* access to config registers.
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*/
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mmio_write_32(PCIE_CONTROL_BASE + PCIE_SECURE_REG, PCIE_SEC_ACCESS_MASK);
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}
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/*******************************************************************************
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* Function which will perform any remaining platform-specific setup that can
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* occur after the MMU and data cache have been enabled.
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******************************************************************************/
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void bl1_platform_setup(void)
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{
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init_nic400();
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init_pcie();
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/* Initialise the IO layer and register platform IO devices */
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io_setup();
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/* Enable and initialize the System level generic timer */
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mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
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}
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/*******************************************************************************
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* Perform the very early platform specific architecture setup here. At the
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* moment this only does basic initialization. Later architectural setup
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* (bl1_arch_setup()) does not do anything platform specific.
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******************************************************************************/
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void bl1_plat_arch_setup(void)
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{
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configure_mmu_el3(bl1_tzram_layout.total_base,
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bl1_tzram_layout.total_size,
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TZROM_BASE,
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TZROM_BASE + TZROM_SIZE
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#if USE_COHERENT_MEM
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, BL1_COHERENT_RAM_BASE,
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BL1_COHERENT_RAM_LIMIT
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#endif
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);
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}
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/*******************************************************************************
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* Before calling this function BL2 is loaded in memory and its entrypoint
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* is set by load_image. This is a placeholder for the platform to change
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* the entrypoint of BL2 and set SPSR and security state.
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* On Juno we are only setting the security state, entrypoint
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******************************************************************************/
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void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image,
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entry_point_info_t *bl2_ep)
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{
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SET_SECURITY_STATE(bl2_ep->h.attr, SECURE);
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bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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}
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