190 lines
5.1 KiB
C
190 lines
5.1 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <cassert.h>
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#include <platform_def.h>
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#include <utils.h>
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#include <utils_def.h>
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#include <xlat_tables_v2.h>
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#include "../xlat_tables_private.h"
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#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)
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#error ARMv7 target does not support LPAE MMU descriptors
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#endif
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uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
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/*
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* Returns 1 if the provided granule size is supported, 0 otherwise.
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*/
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int xlat_arch_is_granule_size_supported(size_t size)
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{
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/*
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* The Trusted Firmware uses long descriptor translation table format,
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* which supports 4 KiB pages only.
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*/
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return (size == (4U * 1024U));
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}
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size_t xlat_arch_get_max_supported_granule_size(void)
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{
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return 4U * 1024U;
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}
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#if ENABLE_ASSERTIONS
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unsigned long long xlat_arch_get_max_supported_pa(void)
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{
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/* Physical address space size for long descriptor format. */
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return (1ULL << 40) - 1ULL;
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}
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#endif /* ENABLE_ASSERTIONS*/
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int is_mmu_enabled_ctx(const xlat_ctx_t *ctx __unused)
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{
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return (read_sctlr() & SCTLR_M_BIT) != 0;
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}
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void xlat_arch_tlbi_va(uintptr_t va)
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{
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/*
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* Ensure the translation table write has drained into memory before
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* invalidating the TLB entry.
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*/
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dsbishst();
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tlbimvaais(TLBI_ADDR(va));
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}
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void xlat_arch_tlbi_va_regime(uintptr_t va, int xlat_regime __unused)
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{
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/*
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* Ensure the translation table write has drained into memory before
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* invalidating the TLB entry.
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*/
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dsbishst();
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tlbimvaais(TLBI_ADDR(va));
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}
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void xlat_arch_tlbi_va_sync(void)
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{
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/* Invalidate all entries from branch predictors. */
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bpiallis();
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/*
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* A TLB maintenance instruction can complete at any time after
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* it is issued, but is only guaranteed to be complete after the
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* execution of DSB by the PE that executed the TLB maintenance
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* instruction. After the TLB invalidate instruction is
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* complete, no new memory accesses using the invalidated TLB
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* entries will be observed by any observer of the system
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* domain. See section D4.8.2 of the ARMv8 (issue k), paragraph
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* "Ordering and completion of TLB maintenance instructions".
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*/
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dsbish();
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/*
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* The effects of a completed TLB maintenance instruction are
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* only guaranteed to be visible on the PE that executed the
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* instruction after the execution of an ISB instruction by the
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* PE that executed the TLB maintenance instruction.
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*/
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isb();
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}
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int xlat_arch_current_el(void)
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{
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/*
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* If EL3 is in AArch32 mode, all secure PL1 modes (Monitor, System,
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* SVC, Abort, UND, IRQ and FIQ modes) execute at EL3.
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*/
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return 3;
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}
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/*******************************************************************************
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* Function for enabling the MMU in Secure PL1, assuming that the page tables
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* have already been created.
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******************************************************************************/
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void setup_mmu_cfg(unsigned int flags,
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const uint64_t *base_table,
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unsigned long long max_pa,
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uintptr_t max_va)
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{
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u_register_t mair0, ttbcr;
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uint64_t ttbr0;
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assert(IS_IN_SECURE());
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/* Set attributes in the right indices of the MAIR */
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mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
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mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
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ATTR_IWBWA_OWBWA_NTR_INDEX);
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mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE,
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ATTR_NON_CACHEABLE_INDEX);
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/*
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* Configure the control register for stage 1 of the PL1&0 translation
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* regime.
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*/
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/* Use the Long-descriptor translation table format. */
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ttbcr = TTBCR_EAE_BIT;
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/*
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* Disable translation table walk for addresses that are translated
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* using TTBR1. Therefore, only TTBR0 is used.
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*/
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ttbcr |= TTBCR_EPD1_BIT;
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/*
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* Limit the input address ranges and memory region sizes translated
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* using TTBR0 to the given virtual address space size, if smaller than
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* 32 bits.
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*/
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if (max_va != UINT32_MAX) {
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uintptr_t virtual_addr_space_size = max_va + 1;
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assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size));
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/*
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* __builtin_ctzll(0) is undefined but here we are guaranteed
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* that virtual_addr_space_size is in the range [1, UINT32_MAX].
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*/
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ttbcr |= 32 - __builtin_ctzll(virtual_addr_space_size);
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}
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/*
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* Set the cacheability and shareability attributes for memory
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* associated with translation table walks using TTBR0.
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*/
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if (flags & XLAT_TABLE_NC) {
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/* Inner & outer non-cacheable non-shareable. */
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ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
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TTBCR_RGN0_INNER_NC;
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} else {
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/* Inner & outer WBWA & shareable. */
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ttbcr |= TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
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TTBCR_RGN0_INNER_WBA;
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}
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/* Set TTBR0 bits as well */
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ttbr0 = (uint64_t)(uintptr_t) base_table;
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#if ARM_ARCH_AT_LEAST(8, 2)
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/*
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* Enable CnP bit so as to share page tables with all PEs.
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* Mandatory for ARMv8.2 implementations.
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*/
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ttbr0 |= TTBR_CNP_BIT;
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#endif
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/* Now populate MMU configuration */
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mmu_cfg_params[MMU_CFG_MAIR0] = mair0;
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mmu_cfg_params[MMU_CFG_TCR] = ttbcr;
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mmu_cfg_params[MMU_CFG_TTBR0_LO] = (uint32_t) ttbr0;
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mmu_cfg_params[MMU_CFG_TTBR0_HI] = ttbr0 >> 32;
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}
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