540 lines
16 KiB
C
540 lines
16 KiB
C
/*
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* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <bl31/bl31.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/smccc.h>
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#include <lib/spinlock.h>
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#include <lib/utils.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/common_def.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <services/spci_svc.h>
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#include <services/spmd_svc.h>
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#include <smccc_helpers.h>
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#include "spmd_private.h"
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/*******************************************************************************
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* SPM Core context information.
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******************************************************************************/
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spmd_spm_core_context_t spm_core_context[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* SPM Core attribute information read from its manifest.
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******************************************************************************/
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static spmc_manifest_sect_attribute_t spmc_attrs;
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/*******************************************************************************
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* SPM Core entry point information. Discovered on the primary core and reused
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* on secondary cores.
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******************************************************************************/
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static entry_point_info_t *spmc_ep_info;
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/*******************************************************************************
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* Static function declaration.
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******************************************************************************/
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static int32_t spmd_init(void);
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static int spmd_spmc_init(void *rd_base, size_t rd_size);
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static uint64_t spmd_spci_error_return(void *handle, int error_code);
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static uint64_t spmd_smc_forward(uint32_t smc_fid, bool secure_origin,
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uint64_t x1, uint64_t x2, uint64_t x3,
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uint64_t x4, void *handle);
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/*******************************************************************************
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* This function takes an SP context pointer and performs a synchronous entry
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* into it.
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******************************************************************************/
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uint64_t spmd_spm_core_sync_entry(spmd_spm_core_context_t *spmc_ctx)
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{
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uint64_t rc;
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assert(spmc_ctx != NULL);
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cm_set_context(&(spmc_ctx->cpu_ctx), SECURE);
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/* Restore the context assigned above */
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cm_el1_sysregs_context_restore(SECURE);
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#if SPMD_SPM_AT_SEL2
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cm_el2_sysregs_context_restore(SECURE);
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#endif
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cm_set_next_eret_context(SECURE);
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/* Enter SPMC */
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rc = spmd_spm_core_enter(&spmc_ctx->c_rt_ctx);
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/* Save secure state */
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cm_el1_sysregs_context_save(SECURE);
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#if SPMD_SPM_AT_SEL2
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cm_el2_sysregs_context_save(SECURE);
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#endif
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return rc;
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}
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/*******************************************************************************
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* This function returns to the place where spm_sp_synchronous_entry() was
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* called originally.
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******************************************************************************/
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__dead2 void spmd_spm_core_sync_exit(uint64_t rc)
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{
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spmd_spm_core_context_t *ctx = &spm_core_context[plat_my_core_pos()];
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/* Get context of the SP in use by this CPU. */
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assert(cm_get_context(SECURE) == &(ctx->cpu_ctx));
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/*
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* The SPMD must have initiated the original request through a
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* synchronous entry into SPMC. Jump back to the original C runtime
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* context with the value of rc in x0;
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*/
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spmd_spm_core_exit(ctx->c_rt_ctx, rc);
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panic();
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}
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/*******************************************************************************
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* Jump to the SPM core for the first time.
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******************************************************************************/
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static int32_t spmd_init(void)
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{
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uint64_t rc = 0;
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spmd_spm_core_context_t *ctx = &spm_core_context[plat_my_core_pos()];
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INFO("SPM Core init start.\n");
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ctx->state = SPMC_STATE_RESET;
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rc = spmd_spm_core_sync_entry(ctx);
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if (rc) {
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ERROR("SPMC initialisation failed 0x%llx\n", rc);
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panic();
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}
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ctx->state = SPMC_STATE_IDLE;
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INFO("SPM Core init end.\n");
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return 1;
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}
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/*******************************************************************************
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* Load SPMC manifest, init SPMC.
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******************************************************************************/
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static int spmd_spmc_init(void *rd_base, size_t rd_size)
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{
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int rc;
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uint32_t ep_attr;
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unsigned int linear_id = plat_my_core_pos();
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spmd_spm_core_context_t *spm_ctx = &spm_core_context[linear_id];
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/* Load the SPM core manifest */
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rc = plat_spm_core_manifest_load(&spmc_attrs, rd_base, rd_size);
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if (rc != 0) {
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WARN("No or invalid SPM core manifest image provided by BL2 "
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"boot loader. ");
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return 1;
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}
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/*
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* Ensure that the SPM core version is compatible with the SPM
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* dispatcher version
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*/
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if ((spmc_attrs.major_version != SPCI_VERSION_MAJOR) ||
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(spmc_attrs.minor_version > SPCI_VERSION_MINOR)) {
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WARN("Unsupported SPCI version (%x.%x) specified in SPM core "
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"manifest image provided by BL2 boot loader.\n",
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spmc_attrs.major_version, spmc_attrs.minor_version);
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return 1;
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}
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INFO("SPCI version (%x.%x).\n", spmc_attrs.major_version,
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spmc_attrs.minor_version);
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INFO("SPM core run time EL%x.\n",
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SPMD_SPM_AT_SEL2 ? MODE_EL2 : MODE_EL1);
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/* Validate the SPMC ID, Ensure high bit is set */
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if (!(spmc_attrs.spmc_id >> SPMC_SECURE_ID_SHIFT) &
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SPMC_SECURE_ID_MASK) {
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WARN("Invalid ID (0x%x) for SPMC.\n",
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spmc_attrs.spmc_id);
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return 1;
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}
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INFO("SPMC ID %x.\n", spmc_attrs.spmc_id);
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/* Validate the SPM core execution state */
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if ((spmc_attrs.exec_state != MODE_RW_64) &&
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(spmc_attrs.exec_state != MODE_RW_32)) {
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WARN("Unsupported SPM core execution state %x specified in "
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"manifest image provided by BL2 boot loader.\n",
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spmc_attrs.exec_state);
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return 1;
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}
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INFO("SPM core execution state %x.\n", spmc_attrs.exec_state);
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#if SPMD_SPM_AT_SEL2
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/* Ensure manifest has not requested AArch32 state in S-EL2 */
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if (spmc_attrs.exec_state == MODE_RW_32) {
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WARN("AArch32 state at S-EL2 is not supported.\n");
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return 1;
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}
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/*
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* Check if S-EL2 is supported on this system if S-EL2
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* is required for SPM
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*/
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uint64_t sel2 = read_id_aa64pfr0_el1();
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sel2 >>= ID_AA64PFR0_SEL2_SHIFT;
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sel2 &= ID_AA64PFR0_SEL2_MASK;
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if (!sel2) {
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WARN("SPM core run time S-EL2 is not supported.");
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return 1;
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}
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#endif /* SPMD_SPM_AT_SEL2 */
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/* Initialise an entrypoint to set up the CPU context */
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ep_attr = SECURE | EP_ST_ENABLE;
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if (read_sctlr_el3() & SCTLR_EE_BIT) {
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ep_attr |= EP_EE_BIG;
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}
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SET_PARAM_HEAD(spmc_ep_info, PARAM_EP, VERSION_1, ep_attr);
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assert(spmc_ep_info->pc == BL32_BASE);
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/*
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* Populate SPSR for SPM core based upon validated parameters from the
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* manifest
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*/
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if (spmc_attrs.exec_state == MODE_RW_32) {
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spmc_ep_info->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
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SPSR_E_LITTLE,
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DAIF_FIQ_BIT |
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DAIF_IRQ_BIT |
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DAIF_ABT_BIT);
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} else {
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#if SPMD_SPM_AT_SEL2
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static const uint32_t runtime_el = MODE_EL2;
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#else
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static const uint32_t runtime_el = MODE_EL1;
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#endif
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spmc_ep_info->spsr = SPSR_64(runtime_el,
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MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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}
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/* Initialise SPM core context with this entry point information */
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cm_setup_context(&spm_ctx->cpu_ctx, spmc_ep_info);
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/* Reuse PSCI affinity states to mark this SPMC context as off */
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spm_ctx->state = AFF_STATE_OFF;
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INFO("SPM core setup done.\n");
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/* Register init function for deferred init. */
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bl31_register_bl32_init(&spmd_init);
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return 0;
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}
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/*******************************************************************************
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* Initialize context of SPM core.
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******************************************************************************/
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int spmd_setup(void)
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{
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int rc;
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void *rd_base;
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size_t rd_size;
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uintptr_t rd_base_align;
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uintptr_t rd_size_align;
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spmc_ep_info = bl31_plat_get_next_image_ep_info(SECURE);
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if (!spmc_ep_info) {
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WARN("No SPM core image provided by BL2 boot loader, Booting "
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"device without SP initialization. SMC`s destined for SPM "
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"core will return SMC_UNK\n");
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return 1;
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}
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/* Under no circumstances will this parameter be 0 */
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assert(spmc_ep_info->pc != 0U);
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/*
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* Check if BL32 ep_info has a reference to 'tos_fw_config'. This will
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* be used as a manifest for the SPM core at the next lower EL/mode.
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*/
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if (spmc_ep_info->args.arg0 == 0U || spmc_ep_info->args.arg2 == 0U) {
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ERROR("Invalid or absent SPM core manifest\n");
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panic();
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}
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/* Obtain whereabouts of SPM core manifest */
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rd_base = (void *) spmc_ep_info->args.arg0;
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rd_size = spmc_ep_info->args.arg2;
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rd_base_align = page_align((uintptr_t) rd_base, DOWN);
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rd_size_align = page_align((uintptr_t) rd_size, UP);
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/* Map the manifest in the SPMD translation regime first */
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VERBOSE("SPM core manifest base : 0x%lx\n", rd_base_align);
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VERBOSE("SPM core manifest size : 0x%lx\n", rd_size_align);
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rc = mmap_add_dynamic_region((unsigned long long) rd_base_align,
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(uintptr_t) rd_base_align,
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rd_size_align,
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MT_RO_DATA);
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if (rc != 0) {
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ERROR("Error while mapping SPM core manifest (%d).\n", rc);
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panic();
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}
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/* Load manifest, init SPMC */
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rc = spmd_spmc_init(rd_base, rd_size);
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if (rc != 0) {
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int mmap_rc;
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WARN("Booting device without SPM initialization. "
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"SPCI SMCs destined for SPM core will return "
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"ENOTSUPPORTED\n");
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mmap_rc = mmap_remove_dynamic_region(rd_base_align,
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rd_size_align);
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if (mmap_rc != 0) {
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ERROR("Error while unmapping SPM core manifest (%d).\n",
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mmap_rc);
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panic();
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}
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return rc;
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}
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return 0;
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}
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/*******************************************************************************
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* Forward SMC to the other security state
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******************************************************************************/
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static uint64_t spmd_smc_forward(uint32_t smc_fid, bool secure_origin,
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uint64_t x1, uint64_t x2, uint64_t x3,
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uint64_t x4, void *handle)
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{
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uint32_t secure_state_in = (secure_origin) ? SECURE : NON_SECURE;
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uint32_t secure_state_out = (!secure_origin) ? SECURE : NON_SECURE;
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/* Save incoming security state */
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cm_el1_sysregs_context_save(secure_state_in);
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#if SPMD_SPM_AT_SEL2
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cm_el2_sysregs_context_save(secure_state_in);
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#endif
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/* Restore outgoing security state */
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cm_el1_sysregs_context_restore(secure_state_out);
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#if SPMD_SPM_AT_SEL2
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cm_el2_sysregs_context_restore(secure_state_out);
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#endif
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cm_set_next_eret_context(secure_state_out);
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SMC_RET8(cm_get_context(secure_state_out), smc_fid, x1, x2, x3, x4,
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SMC_GET_GP(handle, CTX_GPREG_X5),
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SMC_GET_GP(handle, CTX_GPREG_X6),
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SMC_GET_GP(handle, CTX_GPREG_X7));
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}
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/*******************************************************************************
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* Return SPCI_ERROR with specified error code
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******************************************************************************/
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static uint64_t spmd_spci_error_return(void *handle, int error_code)
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{
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SMC_RET8(handle, SPCI_ERROR,
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SPCI_TARGET_INFO_MBZ, error_code,
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SPCI_PARAM_MBZ, SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
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SPCI_PARAM_MBZ, SPCI_PARAM_MBZ);
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}
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/*******************************************************************************
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* This function handles all SMCs in the range reserved for SPCI. Each call is
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* either forwarded to the other security state or handled by the SPM dispatcher
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******************************************************************************/
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uint64_t spmd_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2,
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uint64_t x3, uint64_t x4, void *cookie, void *handle,
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uint64_t flags)
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{
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spmd_spm_core_context_t *ctx = &spm_core_context[plat_my_core_pos()];
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bool secure_origin;
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int32_t ret;
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/* Determine which security state this SMC originated from */
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secure_origin = is_caller_secure(flags);
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INFO("SPM: 0x%x, 0x%llx, 0x%llx, 0x%llx, 0x%llx, "
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"0x%llx, 0x%llx, 0x%llx\n",
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smc_fid, x1, x2, x3, x4, SMC_GET_GP(handle, CTX_GPREG_X5),
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SMC_GET_GP(handle, CTX_GPREG_X6),
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SMC_GET_GP(handle, CTX_GPREG_X7));
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switch (smc_fid) {
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case SPCI_ERROR:
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/*
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* Check if this is the first invocation of this interface on
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* this CPU. If so, then indicate that the SPM core initialised
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* unsuccessfully.
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*/
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if (secure_origin && (ctx->state == SPMC_STATE_RESET)) {
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spmd_spm_core_sync_exit(x2);
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}
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return spmd_smc_forward(smc_fid, secure_origin,
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x1, x2, x3, x4, handle);
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break; /* not reached */
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case SPCI_VERSION:
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/*
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* TODO: This is an optimization that the version information
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* provided by the SPM core manifest is returned by the SPM
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* dispatcher. It might be a better idea to simply forward this
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* call to the SPM core and wash our hands completely.
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*/
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ret = MAKE_SPCI_VERSION(spmc_attrs.major_version,
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spmc_attrs.minor_version);
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SMC_RET8(handle, SPCI_SUCCESS_SMC32, SPCI_TARGET_INFO_MBZ, ret,
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SPCI_PARAM_MBZ, SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
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SPCI_PARAM_MBZ, SPCI_PARAM_MBZ);
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break; /* not reached */
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case SPCI_FEATURES:
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/*
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* This is an optional interface. Do the minimal checks and
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* forward to SPM core which will handle it if implemented.
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*/
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/*
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* Check if x1 holds a valid SPCI fid. This is an
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* optimization.
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*/
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if (!is_spci_fid(x1)) {
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return spmd_spci_error_return(handle,
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SPCI_ERROR_NOT_SUPPORTED);
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}
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/* Forward SMC from Normal world to the SPM core */
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if (!secure_origin) {
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return spmd_smc_forward(smc_fid, secure_origin,
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x1, x2, x3, x4, handle);
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} else {
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/*
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* Return success if call was from secure world i.e. all
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* SPCI functions are supported. This is essentially a
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* nop.
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*/
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SMC_RET8(handle, SPCI_SUCCESS_SMC32, x1, x2, x3, x4,
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SMC_GET_GP(handle, CTX_GPREG_X5),
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SMC_GET_GP(handle, CTX_GPREG_X6),
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SMC_GET_GP(handle, CTX_GPREG_X7));
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}
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break; /* not reached */
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case SPCI_ID_GET:
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/*
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* Returns the ID of the calling SPCI component.
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*/
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if (!secure_origin) {
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SMC_RET8(handle, SPCI_SUCCESS_SMC32,
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SPCI_TARGET_INFO_MBZ, SPCI_NS_ENDPOINT_ID,
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SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
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SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
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SPCI_PARAM_MBZ);
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} else {
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SMC_RET8(handle, SPCI_SUCCESS_SMC32,
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SPCI_TARGET_INFO_MBZ, spmc_attrs.spmc_id,
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SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
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SPCI_PARAM_MBZ, SPCI_PARAM_MBZ,
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SPCI_PARAM_MBZ);
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}
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break; /* not reached */
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case SPCI_RX_RELEASE:
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case SPCI_RXTX_MAP_SMC32:
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case SPCI_RXTX_MAP_SMC64:
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case SPCI_RXTX_UNMAP:
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case SPCI_MSG_RUN:
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/* This interface must be invoked only by the Normal world */
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if (secure_origin) {
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return spmd_spci_error_return(handle,
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SPCI_ERROR_NOT_SUPPORTED);
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}
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/* Fall through to forward the call to the other world */
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case SPCI_PARTITION_INFO_GET:
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case SPCI_MSG_SEND:
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case SPCI_MSG_SEND_DIRECT_REQ_SMC32:
|
|
case SPCI_MSG_SEND_DIRECT_REQ_SMC64:
|
|
case SPCI_MSG_SEND_DIRECT_RESP_SMC32:
|
|
case SPCI_MSG_SEND_DIRECT_RESP_SMC64:
|
|
case SPCI_MEM_DONATE_SMC32:
|
|
case SPCI_MEM_DONATE_SMC64:
|
|
case SPCI_MEM_LEND_SMC32:
|
|
case SPCI_MEM_LEND_SMC64:
|
|
case SPCI_MEM_SHARE_SMC32:
|
|
case SPCI_MEM_SHARE_SMC64:
|
|
case SPCI_MEM_RETRIEVE_REQ_SMC32:
|
|
case SPCI_MEM_RETRIEVE_REQ_SMC64:
|
|
case SPCI_MEM_RETRIEVE_RESP:
|
|
case SPCI_MEM_RELINQUISH:
|
|
case SPCI_MEM_RECLAIM:
|
|
case SPCI_SUCCESS_SMC32:
|
|
case SPCI_SUCCESS_SMC64:
|
|
/*
|
|
* TODO: Assume that no requests originate from EL3 at the
|
|
* moment. This will change if a SP service is required in
|
|
* response to secure interrupts targeted to EL3. Until then
|
|
* simply forward the call to the Normal world.
|
|
*/
|
|
|
|
return spmd_smc_forward(smc_fid, secure_origin,
|
|
x1, x2, x3, x4, handle);
|
|
break; /* not reached */
|
|
|
|
case SPCI_MSG_WAIT:
|
|
/*
|
|
* Check if this is the first invocation of this interface on
|
|
* this CPU from the Secure world. If so, then indicate that the
|
|
* SPM core initialised successfully.
|
|
*/
|
|
if (secure_origin && (ctx->state == SPMC_STATE_RESET)) {
|
|
spmd_spm_core_sync_exit(0);
|
|
}
|
|
|
|
/* Fall through to forward the call to the other world */
|
|
|
|
case SPCI_MSG_YIELD:
|
|
/* This interface must be invoked only by the Secure world */
|
|
if (!secure_origin) {
|
|
return spmd_spci_error_return(handle,
|
|
SPCI_ERROR_NOT_SUPPORTED);
|
|
}
|
|
|
|
return spmd_smc_forward(smc_fid, secure_origin,
|
|
x1, x2, x3, x4, handle);
|
|
break; /* not reached */
|
|
|
|
default:
|
|
WARN("SPM: Unsupported call 0x%08x\n", smc_fid);
|
|
return spmd_spci_error_return(handle, SPCI_ERROR_NOT_SUPPORTED);
|
|
}
|
|
}
|