72 lines
1.4 KiB
ArmAsm
72 lines
1.4 KiB
ArmAsm
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <soc_default_base_addr.h>
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#include <soc_default_helper_macros.h>
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.global ocram_init
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/*
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* void ocram_init(uintptr_t start_addr, size_t size)
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*
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* This function will do OCRAM ECC.
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* OCRAM is initialized with 64-bit writes and then a write
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* performed to address 0x0010_0534 with the value 0x0000_0008.
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*
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* x0: start_addr
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* x1: size in bytes
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* Called from C
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*/
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func ocram_init
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/* save the aarch32/64 non-volatile registers */
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stp x4, x5, [sp, #-16]!
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stp x6, x7, [sp, #-16]!
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stp x8, x9, [sp, #-16]!
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stp x10, x11, [sp, #-16]!
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stp x12, x13, [sp, #-16]!
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stp x18, x30, [sp, #-16]!
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/* convert bytes to 64-byte chunks */
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lsr x1, x1, #6
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1:
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/* for each location, read and write-back */
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dc ivac, x0
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dsb sy
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ldp x4, x5, [x0]
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ldp x6, x7, [x0, #16]
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ldp x8, x9, [x0, #32]
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ldp x10, x11, [x0, #48]
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stp x4, x5, [x0]
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stp x6, x7, [x0, #16]
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stp x8, x9, [x0, #32]
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stp x10, x11, [x0, #48]
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dc cvac, x0
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sub x1, x1, #1
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cbz x1, 2f
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add x0, x0, #64
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b 1b
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2:
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/* Clear OCRAM ECC status bit in SBEESR2 and MBEESR2 */
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ldr w1, =OCRAM_EESR_MASK
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ldr x0, =DCFG_SBEESR2_ADDR
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str w1, [x0]
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ldr x0, =DCFG_MBEESR2_ADDR
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str w1, [x0]
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/* restore the aarch32/64 non-volatile registers */
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ldp x18, x30, [sp], #16
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ldp x12, x13, [sp], #16
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ldp x10, x11, [sp], #16
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ldp x8, x9, [sp], #16
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ldp x6, x7, [sp], #16
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ldp x4, x5, [sp], #16
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ret
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endfunc ocram_init
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