Jeenu Viswambharan 25a93f7cd1 Enable data caches early with hardware-assisted coherency ... At present, warm-booted CPUs keep their caches disabled when enabling MMU, and remains so until they enter coherency later. On systems with hardware-assisted coherency, for which HW_ASSISTED_COHERENCY build flag would be enabled, warm-booted CPUs can have both caches and MMU enabled at once. Change-Id: Icb0adb026e01aecf34beadf49c88faa9dd368327 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>		2017-03-02 11:00:20 +00:00
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aarch64	Enable data caches early with hardware-assisted coherency	2017-03-02 11:00:20 +00:00
bl31.ld.S	Introduce unified API to zero memory	2017-02-06 17:01:39 +00:00
bl31.mk	Introduce PSCI Library Interface	2016-07-19 10:19:01 +01:00
bl31_context_mgmt.c	Introduce `el3_runtime` and `PSCI` libraries	2016-07-18 17:52:15 +01:00
bl31_main.c	Add PMF instrumentation points in TF	2016-10-12 15:36:49 +01:00
interrupt_mgmt.c	Enable support for EL3 interrupt in IMF	2015-12-09 09:58:17 +00:00