Harvey Hsieh b495791ba2 Tegra: support to set the L2 ECC and Parity enable bit ... This patch adds capability to read the boot flag to enable L2 ECC and Parity Protection bit for the Cortex-A57 CPUs. The previous bootloader sets this flag value for the platform. * with some coverity fix: MISRA C-2012 Directive 4.6 MISRA C-2012 Rule 2.5 MISRA C-2012 Rule 10.3 MISRA C-2012 Rule 10.4 Change-Id: Id7303bbbdc290b52919356c31625847b8904b073 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>		2019-01-16 10:10:52 -08:00
..
allwinner	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
arm	Merge pull request #1738 from ardbiesheuvel/synquacer-spm	2019-01-16 16:01:42 +00:00
common	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
hisilicon	Move BL1 and BL2 private defines to bl_common.h	2019-01-15 13:52:32 +00:00
imx	imx: make imx uart work for debug mode	2019-01-15 14:32:31 +08:00
layerscape	Move BL1 and BL2 private defines to bl_common.h	2019-01-15 13:52:32 +00:00
marvell	Move BL1 and BL2 private defines to bl_common.h	2019-01-15 13:52:32 +00:00
mediatek	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
meson/gxbb	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
nvidia/tegra	Tegra: support to set the L2 ECC and Parity enable bit	2019-01-16 10:10:52 -08:00
qemu	Move BL1 and BL2 private defines to bl_common.h	2019-01-15 13:52:32 +00:00
renesas/rcar	rcar_gen3: plat: update renesas version to 2.0.0	2019-01-08 14:08:44 +01:00
rockchip	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
rpi3	Move BL1 and BL2 private defines to bl_common.h	2019-01-15 13:52:32 +00:00
socionext	plat/synquacer: enable SPM support	2019-01-15 17:51:23 +01:00
st/stm32mp1	stm32mp1: do not include platform header files directly in drivers	2019-01-07 11:17:24 +01:00
ti/k3	Sanitise includes across codebase	2019-01-04 10:43:17 +00:00
xilinx	xilinx: Move IPI functions to common file	2019-01-09 12:38:00 -08:00