83 lines
2.3 KiB
C
83 lines
2.3 KiB
C
/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <lib/mmio.h>
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#include "agilex_reset_manager.h"
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void deassert_peripheral_reset(void)
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{
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mmio_clrbits_32(AGX_RSTMGR_PER1MODRST,
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AGX_RSTMGR_PER1MODRST_WATCHDOG0 |
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AGX_RSTMGR_PER1MODRST_WATCHDOG1 |
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AGX_RSTMGR_PER1MODRST_WATCHDOG2 |
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AGX_RSTMGR_PER1MODRST_WATCHDOG3 |
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AGX_RSTMGR_PER1MODRST_L4SYSTIMER0 |
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AGX_RSTMGR_PER1MODRST_L4SYSTIMER1 |
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AGX_RSTMGR_PER1MODRST_SPTIMER0 |
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AGX_RSTMGR_PER1MODRST_SPTIMER1 |
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AGX_RSTMGR_PER1MODRST_I2C0 |
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AGX_RSTMGR_PER1MODRST_I2C1 |
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AGX_RSTMGR_PER1MODRST_I2C2 |
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AGX_RSTMGR_PER1MODRST_I2C3 |
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AGX_RSTMGR_PER1MODRST_I2C4 |
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AGX_RSTMGR_PER1MODRST_UART0 |
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AGX_RSTMGR_PER1MODRST_UART1 |
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AGX_RSTMGR_PER1MODRST_GPIO0 |
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AGX_RSTMGR_PER1MODRST_GPIO1);
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mmio_clrbits_32(AGX_RSTMGR_PER0MODRST,
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AGX_RSTMGR_PER0MODRST_EMAC0OCP |
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AGX_RSTMGR_PER0MODRST_EMAC1OCP |
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AGX_RSTMGR_PER0MODRST_EMAC2OCP |
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AGX_RSTMGR_PER0MODRST_USB0OCP |
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AGX_RSTMGR_PER0MODRST_USB1OCP |
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AGX_RSTMGR_PER0MODRST_NANDOCP |
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AGX_RSTMGR_PER0MODRST_SDMMCOCP |
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AGX_RSTMGR_PER0MODRST_DMAOCP);
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mmio_clrbits_32(AGX_RSTMGR_PER0MODRST,
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AGX_RSTMGR_PER0MODRST_EMAC0 |
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AGX_RSTMGR_PER0MODRST_EMAC1 |
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AGX_RSTMGR_PER0MODRST_EMAC2 |
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AGX_RSTMGR_PER0MODRST_USB0 |
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AGX_RSTMGR_PER0MODRST_USB1 |
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AGX_RSTMGR_PER0MODRST_NAND |
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AGX_RSTMGR_PER0MODRST_SDMMC |
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AGX_RSTMGR_PER0MODRST_DMA |
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AGX_RSTMGR_PER0MODRST_SPIM0 |
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AGX_RSTMGR_PER0MODRST_SPIM1 |
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AGX_RSTMGR_PER0MODRST_SPIS0 |
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AGX_RSTMGR_PER0MODRST_SPIS1 |
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AGX_RSTMGR_PER0MODRST_EMACPTP |
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AGX_RSTMGR_PER0MODRST_DMAIF0 |
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AGX_RSTMGR_PER0MODRST_DMAIF1 |
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AGX_RSTMGR_PER0MODRST_DMAIF2 |
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AGX_RSTMGR_PER0MODRST_DMAIF3 |
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AGX_RSTMGR_PER0MODRST_DMAIF4 |
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AGX_RSTMGR_PER0MODRST_DMAIF5 |
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AGX_RSTMGR_PER0MODRST_DMAIF6 |
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AGX_RSTMGR_PER0MODRST_DMAIF7);
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mmio_clrbits_32(AGX_RSTMGR_BRGMODRST,
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AGX_RSTMGR_BRGMODRST_MPFE);
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}
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void config_hps_hs_before_warm_reset(void)
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{
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uint32_t or_mask = 0;
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or_mask |= AGX_RSTMGR_HDSKEN_SDRSELFREFEN;
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or_mask |= AGX_RSTMGR_HDSKEN_FPGAHSEN;
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or_mask |= AGX_RSTMGR_HDSKEN_ETRSTALLEN;
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or_mask |= AGX_RSTMGR_HDSKEN_L2FLUSHEN;
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or_mask |= AGX_RSTMGR_HDSKEN_L3NOC_DBG;
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or_mask |= AGX_RSTMGR_HDSKEN_DEBUG_L3NOC;
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mmio_setbits_32(AGX_RSTMGR_HDSKEN, or_mask);
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}
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