Andrew F. Davis 6a655a85c0 ti: k3: common: Do not disable cache on TI K3 core powerdown ... Leave the caches on and explicitly flush any data that may be stale when the core is powered down. This prevents non-coherent interconnect access which has negative side- effects on AM65x. Signed-off-by: Andrew F. Davis <afd@ti.com>		2018-10-16 09:27:53 -05:00
..
aarch32	aarch32: Implement static workaround for CVE-2018-3639	2018-05-23 12:45:48 +01:00
aarch64	ti: k3: common: Do not disable cache on TI K3 core powerdown	2018-10-16 09:27:53 -05:00
cpu-ops.mk	DSU erratum 936184 workaround	2018-08-17 10:34:43 +01:00
errata_report.c	Merge pull request #1228 from dp-arm/dp/cve_2017_5715	2018-01-25 00:06:50 +00:00