Varun Wadekar fbc44bd1bb Prevent RAS register access from lower ELs ... This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register accesses from EL1 or EL2 to EL3. RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438		2020-06-12 10:20:11 -07:00
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tbbr	cert_create: add SiP owned secure partitions support	2020-06-08 22:42:06 +01:00
armv7-a-cpus.mk	plat/arm: Support for Cortex A5 in FVP Versatile Express platform	2019-02-19 17:07:48 +00:00
build_env.mk	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
build_macros.mk	Build: introduce per-BL CPPFLAGS and ASFLAGS	2020-03-31 16:08:21 +09:00
cygwin.mk	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
defaults.mk	Prevent RAS register access from lower ELs	2020-06-12 10:20:11 -07:00
msys.mk	Use SPDX license identifiers	2017-05-03 09:39:28 +01:00
plat_helpers.mk	Change PLATFORM_ROOT to TF_PLATFORM_ROOT	2018-03-05 14:18:04 +08:00
unix.mk	Makefile: Fix verbose builds on Windows	2018-10-19 15:54:27 +01:00
windows.mk	Makefile: Fix verbose builds on Windows	2018-10-19 15:54:27 +01:00