395 lines
13 KiB
C
395 lines
13 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl31.h>
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#include <bl_common.h>
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#include <console.h>
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#include <cortex_a57.h>
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#include <cortex_a53.h>
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#include <debug.h>
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#include <denver.h>
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#include <errno.h>
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#include <memctrl.h>
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#include <mmio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <stddef.h>
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#include <string.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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extern void zeromem16(void *mem, unsigned int length);
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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* of trusted SRAM
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******************************************************************************/
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extern unsigned long __TEXT_START__;
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extern unsigned long __TEXT_END__;
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extern unsigned long __RW_START__;
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extern unsigned long __RW_END__;
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extern unsigned long __RODATA_START__;
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extern unsigned long __RODATA_END__;
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extern unsigned long __BL31_END__;
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extern uint64_t tegra_bl31_phys_base;
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extern uint64_t tegra_console_base;
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/*
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* The next 3 constants identify the extents of the code, RO data region and the
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* limit of the BL3-1 image. These addresses are used by the MMU setup code and
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* therefore they must be page-aligned. It is the responsibility of the linker
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* script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
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* refer to page-aligned addresses.
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*/
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#define BL31_RW_START (unsigned long)(&__RW_START__)
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#define BL31_RW_END (unsigned long)(&__RW_END__)
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#define BL31_RODATA_BASE (unsigned long)(&__RODATA_START__)
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#define BL31_RODATA_END (unsigned long)(&__RODATA_END__)
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#define BL31_END (unsigned long)(&__BL31_END__)
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static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
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static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
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.tzdram_size = (uint64_t)TZDRAM_SIZE
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};
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/*******************************************************************************
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* This variable holds the non-secure image entry address
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******************************************************************************/
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extern uint64_t ns_image_entrypoint;
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/*******************************************************************************
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* The following platform setup functions are weakly defined. They
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* provide typical implementations that will be overridden by a SoC.
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******************************************************************************/
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#pragma weak plat_early_platform_setup
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#pragma weak plat_get_bl31_params
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#pragma weak plat_get_bl31_plat_params
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void plat_early_platform_setup(void)
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{
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; /* do nothing */
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}
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bl31_params_t *plat_get_bl31_params(void)
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{
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return NULL;
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}
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plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
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{
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return NULL;
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}
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type.
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******************************************************************************/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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if (type == NON_SECURE)
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return &bl33_image_ep_info;
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/* return BL32 entry point info if it is valid */
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if (type == SECURE && bl32_image_ep_info.pc)
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return &bl32_image_ep_info;
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return NULL;
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}
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/*******************************************************************************
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* Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
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* passes this platform specific information.
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******************************************************************************/
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plat_params_from_bl2_t *bl31_get_plat_params(void)
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{
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return &plat_bl31_params_from_bl2;
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}
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/*******************************************************************************
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* Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
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* info.
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******************************************************************************/
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void bl31_early_platform_setup(bl31_params_t *from_bl2,
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void *plat_params_from_bl2)
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{
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plat_params_from_bl2_t *plat_params =
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(plat_params_from_bl2_t *)plat_params_from_bl2;
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#if DEBUG
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int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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#endif
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image_info_t bl32_img_info = { {0} };
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uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
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/*
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* For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
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* there's no argument to relay from a previous bootloader. Platforms
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* might use custom ways to get arguments, so provide handlers which
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* they can override.
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*/
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if (from_bl2 == NULL)
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from_bl2 = plat_get_bl31_params();
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if (plat_params == NULL)
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plat_params = plat_get_bl31_plat_params();
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/*
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* Copy BL3-3, BL3-2 entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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assert(from_bl2);
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assert(from_bl2->bl33_ep_info);
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bl33_image_ep_info = *from_bl2->bl33_ep_info;
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if (from_bl2->bl32_ep_info)
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bl32_image_ep_info = *from_bl2->bl32_ep_info;
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/*
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* Parse platform specific parameters - TZDRAM aperture base and size
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*/
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assert(plat_params);
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plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
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plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
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plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
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/*
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* It is very important that we run either from TZDRAM or TZSRAM base.
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* Add an explicit check here.
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*/
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if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) &&
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(TEGRA_TZRAM_BASE != BL31_BASE))
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panic();
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/*
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* Get the base address of the UART controller to be used for the
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* console
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*/
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tegra_console_base = plat_get_console_from_id(plat_params->uart_id);
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if (tegra_console_base != (uint64_t)0) {
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/*
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* Configure the UART port to be used as the console
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*/
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console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
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TEGRA_CONSOLE_BAUDRATE);
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/* Initialise crash console */
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plat_crash_console_init();
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}
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/*
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* Do initial security configuration to allow DRAM/device access.
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*/
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tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
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plat_bl31_params_from_bl2.tzdram_size);
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/*
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* The previous bootloader might not have placed the BL32 image
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* inside the TZDRAM. We check the BL32 image info to find out
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* the base/PC values and relocate the image if necessary.
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*/
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if (from_bl2->bl32_image_info) {
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bl32_img_info = *from_bl2->bl32_image_info;
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/* Relocate BL32 if it resides outside of the TZDRAM */
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tzdram_start = plat_bl31_params_from_bl2.tzdram_base;
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tzdram_end = plat_bl31_params_from_bl2.tzdram_base +
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plat_bl31_params_from_bl2.tzdram_size;
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bl32_start = bl32_img_info.image_base;
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bl32_end = bl32_img_info.image_base + bl32_img_info.image_size;
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assert(tzdram_end > tzdram_start);
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assert(bl32_end > bl32_start);
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assert(bl32_image_ep_info.pc > tzdram_start);
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assert(bl32_image_ep_info.pc < tzdram_end);
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/* relocate BL32 */
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if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) {
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INFO("Relocate BL32 to TZDRAM\n");
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memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
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(void *)(uintptr_t)bl32_start,
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bl32_img_info.image_size);
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/* clean up non-secure intermediate buffer */
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zeromem16((void *)(uintptr_t)bl32_start,
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bl32_img_info.image_size);
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}
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}
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/* Early platform setup for Tegra SoCs */
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plat_early_platform_setup();
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INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ?
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"Denver" : "ARM", read_mpidr());
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}
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/*******************************************************************************
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* Initialize the gic, configure the SCR.
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******************************************************************************/
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void bl31_platform_setup(void)
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{
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uint32_t tmp_reg;
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/* Initialize the gic cpu and distributor interfaces */
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plat_gic_setup();
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/*
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* Initialize delay timer
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*/
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tegra_delay_timer_init();
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/*
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* Setup secondary CPU POR infrastructure.
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*/
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plat_secondary_setup();
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/*
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* Initial Memory Controller configuration.
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*/
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tegra_memctrl_setup();
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/*
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* Set up the TZRAM memory aperture to allow only secure world
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* access
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*/
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tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
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/* Set the next EL to be AArch64 */
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tmp_reg = SCR_RES1_BITS | SCR_RW_BIT;
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write_scr(tmp_reg);
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INFO("BL3-1: Tegra platform setup complete\n");
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}
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/*******************************************************************************
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* Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit
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******************************************************************************/
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void bl31_plat_runtime_setup(void)
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{
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; /* do nothing */
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this only intializes the mmu in a quick and dirty way.
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******************************************************************************/
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void bl31_plat_arch_setup(void)
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{
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unsigned long rw_start = BL31_RW_START;
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unsigned long rw_size = BL31_RW_END - BL31_RW_START;
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unsigned long rodata_start = BL31_RODATA_BASE;
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unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
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unsigned long code_base = (unsigned long)(&__TEXT_START__);
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unsigned long code_size = (unsigned long)(&__TEXT_END__) - code_base;
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const mmap_region_t *plat_mmio_map = NULL;
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#if USE_COHERENT_MEM
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unsigned long coh_start, coh_size;
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#endif
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plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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/* add memory regions */
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mmap_add_region(rw_start, rw_start,
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rw_size,
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MT_MEMORY | MT_RW | MT_SECURE);
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mmap_add_region(rodata_start, rodata_start,
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rodata_size,
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MT_RO_DATA | MT_SECURE);
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mmap_add_region(code_base, code_base,
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code_size,
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MT_CODE | MT_SECURE);
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/* map TZDRAM used by BL31 as coherent memory */
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if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
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mmap_add_region(params_from_bl2->tzdram_base,
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params_from_bl2->tzdram_base,
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BL31_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE);
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}
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#if USE_COHERENT_MEM
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coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
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coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
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mmap_add_region(coh_start, coh_start,
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coh_size,
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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/* add MMIO space */
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plat_mmio_map = plat_get_mmio_map();
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if (plat_mmio_map)
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mmap_add(plat_mmio_map);
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else
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WARN("MMIO map not available\n");
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/* set up translation tables */
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init_xlat_tables();
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/* enable the MMU */
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enable_mmu_el3(0);
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INFO("BL3-1: Tegra: MMU enabled\n");
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}
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/*******************************************************************************
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* Check if the given NS DRAM range is valid
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******************************************************************************/
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int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
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{
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uint64_t end = base + size_in_bytes - 1;
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/*
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* Check if the NS DRAM address is valid
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*/
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if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) ||
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(base >= end)) {
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ERROR("NS address is out-of-bounds!\n");
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return -EFAULT;
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}
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/*
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* TZDRAM aperture contains the BL31 and BL32 images, so we need
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* to check if the NS DRAM range overlaps the TZDRAM aperture.
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*/
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if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) {
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ERROR("NS address overlaps TZDRAM!\n");
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return -ENOTSUP;
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}
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/* valid NS address */
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return 0;
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}
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