346 lines
12 KiB
C
346 lines
12 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <arm_gic.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <gic_v2.h>
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#include <interrupt_mgmt.h>
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#include <platform.h>
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#include <stdint.h>
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#include <tegra_private.h>
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#include <tegra_def.h>
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/* Value used to initialize Non-Secure IRQ priorities four at a time */
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#define GICD_IPRIORITYR_DEF_VAL \
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(GIC_HIGHEST_NS_PRIORITY | \
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(GIC_HIGHEST_NS_PRIORITY << 8) | \
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(GIC_HIGHEST_NS_PRIORITY << 16) | \
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(GIC_HIGHEST_NS_PRIORITY << 24))
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static const irq_sec_cfg_t *g_irq_sec_ptr;
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static unsigned int g_num_irqs;
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/*******************************************************************************
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* Place the cpu interface in a state where it can never make a cpu exit wfi as
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* as result of an asserted interrupt. This is critical for powering down a cpu
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******************************************************************************/
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void tegra_gic_cpuif_deactivate(void)
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{
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unsigned int val;
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/* Disable secure, non-secure interrupts and disable their bypass */
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val = gicc_read_ctlr(TEGRA_GICC_BASE);
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val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
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gicc_write_ctlr(TEGRA_GICC_BASE, val);
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}
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/*******************************************************************************
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* Enable secure interrupts and set the priority mask register to allow all
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* interrupts to trickle in.
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******************************************************************************/
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static void tegra_gic_cpuif_setup(unsigned int gicc_base)
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{
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unsigned int val;
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val = ENABLE_GRP0 | ENABLE_GRP1 | FIQ_EN | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
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gicc_write_ctlr(gicc_base, val);
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gicc_write_pmr(gicc_base, GIC_PRI_MASK);
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}
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/*******************************************************************************
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* Per cpu gic distributor setup which will be done by all cpus after a cold
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* boot/hotplug. This marks out the secure interrupts & enables them.
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******************************************************************************/
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static void tegra_gic_pcpu_distif_setup(unsigned int gicd_base)
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{
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unsigned int index, sec_ppi_sgi_mask = 0;
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assert(gicd_base);
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/* Setup PPI priorities doing four at a time */
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for (index = 0; index < 32; index += 4) {
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gicd_write_ipriorityr(gicd_base, index,
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GICD_IPRIORITYR_DEF_VAL);
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}
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/*
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* Invert the bitmask to create a mask for non-secure PPIs and
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* SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will
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* update the GICR_IGROUPR0 as well in case we are running on a GICv3
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* system. This is critical if GICD_CTLR.ARE_NS=1.
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*/
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gicd_write_igroupr(gicd_base, 0, ~sec_ppi_sgi_mask);
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}
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/*******************************************************************************
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* Global gic distributor setup which will be done by the primary cpu after a
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* cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them.
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* It then enables the secure GIC distributor interface.
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******************************************************************************/
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static void tegra_gic_distif_setup(unsigned int gicd_base)
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{
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unsigned int index, num_ints, irq_num;
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uint8_t target_cpus;
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uint32_t val;
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/*
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* Mark out non-secure interrupts. Calculate number of
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* IGROUPR registers to consider. Will be equal to the
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* number of IT_LINES
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*/
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num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
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num_ints = (num_ints + 1) << 5;
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for (index = MIN_SPI_ID; index < num_ints; index += 32)
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gicd_write_igroupr(gicd_base, index, ~0);
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/* Setup SPI priorities doing four at a time */
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for (index = MIN_SPI_ID; index < num_ints; index += 4) {
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gicd_write_ipriorityr(gicd_base, index,
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GICD_IPRIORITYR_DEF_VAL);
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}
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/* Configure SPI secure interrupts now */
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if (g_irq_sec_ptr) {
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for (index = 0; index < g_num_irqs; index++) {
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irq_num = (g_irq_sec_ptr + index)->irq;
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target_cpus = (g_irq_sec_ptr + index)->target_cpus;
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if (irq_num >= MIN_SPI_ID) {
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/* Configure as a secure interrupt */
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gicd_clr_igroupr(gicd_base, irq_num);
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/* Configure SPI priority */
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mmio_write_8(gicd_base + GICD_IPRIORITYR +
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irq_num,
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GIC_HIGHEST_SEC_PRIORITY &
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GIC_PRI_MASK);
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/* Configure as level triggered */
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val = gicd_read_icfgr(gicd_base, irq_num);
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val |= (3 << ((irq_num & 0xF) << 1));
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gicd_write_icfgr(gicd_base, irq_num, val);
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/* Route SPI to the target CPUs */
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gicd_set_itargetsr(gicd_base, irq_num,
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target_cpus);
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/* Enable this interrupt */
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gicd_set_isenabler(gicd_base, irq_num);
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}
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}
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}
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/*
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* Configure the SGI and PPI. This is done in a separated function
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* because each CPU is responsible for initializing its own private
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* interrupts.
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*/
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tegra_gic_pcpu_distif_setup(gicd_base);
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/* enable distributor */
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gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1);
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}
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void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, unsigned int num_irqs)
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{
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g_irq_sec_ptr = irq_sec_ptr;
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g_num_irqs = num_irqs;
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tegra_gic_cpuif_setup(TEGRA_GICC_BASE);
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tegra_gic_distif_setup(TEGRA_GICD_BASE);
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}
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/*******************************************************************************
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* An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
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* The interrupt controller knows which pin/line it uses to signal a type of
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* interrupt. This function provides a common implementation of
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* plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use
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* across platforms. It lets the interrupt management framework determine
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* for a type of interrupt and security state, which line should be used in the
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* SCR_EL3 to control its routing to EL3. The interrupt line is represented as
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* the bit position of the IRQ or FIQ bit in the SCR_EL3.
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******************************************************************************/
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uint32_t tegra_gic_interrupt_type_to_line(uint32_t type,
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uint32_t security_state)
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{
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assert(type == INTR_TYPE_S_EL1 ||
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type == INTR_TYPE_EL3 ||
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type == INTR_TYPE_NS);
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assert(sec_state_is_valid(security_state));
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/*
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* We ignore the security state parameter under the assumption that
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* both normal and secure worlds are using ARM GICv2. This parameter
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* will be used when the secure world starts using GICv3.
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*/
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#if ARM_GIC_ARCH == 2
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return gicv2_interrupt_type_to_line(TEGRA_GICC_BASE, type);
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#else
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#error "Invalid ARM GIC architecture version specified for platform port"
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#endif /* ARM_GIC_ARCH */
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}
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#if ARM_GIC_ARCH == 2
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/*******************************************************************************
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* This function returns the type of the highest priority pending interrupt at
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* the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
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* interrupt pending.
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******************************************************************************/
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uint32_t tegra_gic_get_pending_interrupt_type(void)
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{
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uint32_t id;
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unsigned int index;
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id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK;
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/* get the interrupt type */
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if (id < 1022) {
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for (index = 0; index < g_num_irqs; index++) {
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if (id == (g_irq_sec_ptr + index)->irq)
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return (g_irq_sec_ptr + index)->type;
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}
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}
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if (id == GIC_SPURIOUS_INTERRUPT)
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return INTR_TYPE_INVAL;
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return INTR_TYPE_NS;
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}
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/*******************************************************************************
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* This function returns the id of the highest priority pending interrupt at
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* the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
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* interrupt pending.
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******************************************************************************/
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uint32_t tegra_gic_get_pending_interrupt_id(void)
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{
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uint32_t id;
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id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK;
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if (id < 1022)
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return id;
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if (id == 1023)
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return INTR_ID_UNAVAILABLE;
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/*
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* Find out which non-secure interrupt it is under the assumption that
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* the GICC_CTLR.AckCtl bit is 0.
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*/
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return gicc_read_ahppir(TEGRA_GICC_BASE) & INT_ID_MASK;
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}
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/*******************************************************************************
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* This functions reads the GIC cpu interface Interrupt Acknowledge register
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* to start handling the pending interrupt. It returns the contents of the IAR.
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******************************************************************************/
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uint32_t tegra_gic_acknowledge_interrupt(void)
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{
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return gicc_read_IAR(TEGRA_GICC_BASE);
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}
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/*******************************************************************************
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* This functions writes the GIC cpu interface End Of Interrupt register with
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* the passed value to finish handling the active interrupt
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******************************************************************************/
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void tegra_gic_end_of_interrupt(uint32_t id)
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{
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gicc_write_EOIR(TEGRA_GICC_BASE, id);
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}
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/*******************************************************************************
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* This function returns the type of the interrupt id depending upon the group
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* this interrupt has been configured under by the interrupt controller i.e.
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* group0 or group1.
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******************************************************************************/
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uint32_t tegra_gic_get_interrupt_type(uint32_t id)
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{
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uint32_t group;
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unsigned int index;
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group = gicd_get_igroupr(TEGRA_GICD_BASE, id);
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/* get the interrupt type */
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if (group == GRP0) {
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for (index = 0; index < g_num_irqs; index++) {
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if (id == (g_irq_sec_ptr + index)->irq)
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return (g_irq_sec_ptr + index)->type;
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}
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}
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return INTR_TYPE_NS;
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}
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#else
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#error "Invalid ARM GIC architecture version specified for platform port"
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#endif /* ARM_GIC_ARCH */
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uint32_t plat_ic_get_pending_interrupt_id(void)
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{
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return tegra_gic_get_pending_interrupt_id();
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}
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uint32_t plat_ic_get_pending_interrupt_type(void)
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{
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return tegra_gic_get_pending_interrupt_type();
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}
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uint32_t plat_ic_acknowledge_interrupt(void)
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{
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return tegra_gic_acknowledge_interrupt();
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}
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uint32_t plat_ic_get_interrupt_type(uint32_t id)
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{
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return tegra_gic_get_interrupt_type(id);
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}
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void plat_ic_end_of_interrupt(uint32_t id)
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{
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tegra_gic_end_of_interrupt(id);
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}
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uint32_t plat_interrupt_type_to_line(uint32_t type,
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uint32_t security_state)
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{
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return tegra_gic_interrupt_type_to_line(type, security_state);
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}
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