165 lines
4.8 KiB
C
165 lines
4.8 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <errno.h>
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#include <memctrl.h>
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#include <runtime_svc.h>
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#include <tegra_private.h>
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/*******************************************************************************
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* Common Tegra SiP SMCs
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******************************************************************************/
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#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
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#define TEGRA_SIP_FIQ_NS_ENTRYPOINT 0x82000005
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#define TEGRA_SIP_FIQ_NS_GET_CONTEXT 0x82000006
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/*******************************************************************************
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* SoC specific SiP handler
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******************************************************************************/
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#pragma weak plat_sip_handler
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int plat_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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void *cookie,
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void *handle,
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uint64_t flags)
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{
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return -ENOTSUP;
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}
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/*******************************************************************************
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* This function is responsible for handling all SiP calls
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******************************************************************************/
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uint64_t tegra_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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void *cookie,
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void *handle,
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uint64_t flags)
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{
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int err;
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/* Check if this is a SoC specific SiP */
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err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
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if (err == 0)
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SMC_RET1(handle, err);
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switch (smc_fid) {
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case TEGRA_SIP_NEW_VIDEOMEM_REGION:
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/* clean up the high bits */
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x2 = (uint32_t)x2;
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/*
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* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
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* or falls outside of the valid DRAM range
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*/
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err = bl31_check_ns_address(x1, x2);
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if (err)
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SMC_RET1(handle, err);
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/*
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* Check if Video Memory is aligned to 1MB.
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*/
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if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) {
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ERROR("Unaligned Video Memory base address!\n");
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SMC_RET1(handle, -ENOTSUP);
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}
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/* new video memory carveout settings */
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tegra_memctrl_videomem_setup(x1, x2);
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SMC_RET1(handle, 0);
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break;
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/*
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* The NS world registers the address of its handler to be
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* used for processing the FIQ. This is normally used by the
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* NS FIQ debugger driver to detect system hangs by programming
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* a watchdog timer to fire a FIQ interrupt.
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*/
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case TEGRA_SIP_FIQ_NS_ENTRYPOINT:
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if (!x1)
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SMC_RET1(handle, SMC_UNK);
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/*
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* TODO: Check if x1 contains a valid DRAM address
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*/
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/* store the NS world's entrypoint */
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tegra_fiq_set_ns_entrypoint(x1);
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SMC_RET1(handle, 0);
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break;
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/*
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* The NS world's FIQ handler issues this SMC to get the NS EL1/EL0
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* CPU context when the FIQ interrupt was triggered. This allows the
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* NS world to understand the CPU state when the watchdog interrupt
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* triggered.
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*/
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case TEGRA_SIP_FIQ_NS_GET_CONTEXT:
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/* retrieve context registers when FIQ triggered */
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tegra_fiq_get_intr_context();
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SMC_RET0(handle);
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break;
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default:
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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break;
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}
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SMC_RET1(handle, SMC_UNK);
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}
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/* Define a runtime service descriptor for fast SMC calls */
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DECLARE_RT_SVC(
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tegra_sip_fast,
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OEN_SIP_START,
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OEN_SIP_END,
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SMC_TYPE_FAST,
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NULL,
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tegra_sip_handler
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);
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