71 lines
1.8 KiB
C
71 lines
1.8 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef SOC_DEFAULT_BASE_ADDR_H
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#define SOC_DEFAULT_BASE_ADDR_H
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/* CCSR mmu_def.h */
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#define NXP_CCSR_ADDR 0x01000000
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#define NXP_CCSR_SIZE 0x0F000000
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#define NXP_DCSR_ADDR 0x20000000
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#define NXP_DCSR_SIZE 0x4000000
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/* Flex-SPI controller address */
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#define NXP_FLEXSPI_ADDR 0x020C0000
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/* QSPI Flash Start address */
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#define NXP_QSPI_FLASH_ADDR 0x40000000
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/* NOR Flash Start address */
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#define NXP_IFC_REGION_ADDR 0x60000000
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#define NXP_NOR_FLASH_ADDR NXP_IFC_REGION_ADDR
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/* MMU 500 soc.c*/
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#define NXP_SMMU_ADDR 0x09000000
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#define NXP_SNVS_ADDR 0x01E90000
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#define NXP_DCFG_ADDR 0x01EE0000
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#define NXP_SFP_ADDR 0x01E80000
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#define NXP_RCPM_ADDR 0x01EE2000
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#define NXP_CSU_ADDR 0x01510000
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#define NXP_IFC_ADDR 0x01530000
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#define NXP_SCFG_ADDR 0x01570000
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#define NXP_DCSR_ADDR 0x20000000
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#define NXP_DCSR_DCFG_ADDR (NXP_DCSR_ADDR + 0x00140000)
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#define NXP_I2C_ADDR 0x02180000
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#define NXP_ESDHC_ADDR 0x01560000
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#define NXP_UART_ADDR 0x021C0500
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#define NXP_UART1_ADDR 0x021C0600
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#define NXP_GPIO1_ADDR 0x02300000
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#define NXP_GPIO2_ADDR 0x02310000
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#define NXP_GPIO3_ADDR 0x02320000
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#define NXP_GPIO4_ADDR 0x02330000
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#define NXP_WDOG1_NS_ADDR 0x02390000
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#define NXP_WDOG2_NS_ADDR 0x023A0000
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#define NXP_WDOG1_TZ_ADDR 0x023B0000
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#define NXP_WDOG2_TZ_ADDR 0x023C0000
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#define NXP_TIMER_STATUS_ADDR 0x023F0000
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#define NXP_GICD_4K_ADDR 0x01401000
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#define NXP_GICC_4K_ADDR 0x01402000
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#define NXP_GICD_64K_ADDR 0x01410000
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#define NXP_GICC_64K_ADDR 0x01420000
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#define NXP_CAAM_ADDR 0x01700000
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#define NXP_TZC_ADDR 0x01500000
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#define NXP_DDR_ADDR 0x01080000
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#define NXP_TIMER_ADDR 0x02B00000
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#define NXP_CCI_ADDR 0x01180000
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#define NXP_RESET_ADDR 0x01E60000
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#define NXP_SEC_REGFILE_ADDR 0x01E88000
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#endif /* SOC_DEFAULT_BASE_ADDR_H */
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