71 lines
1.5 KiB
C
71 lines
1.5 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <cpuamu.h>
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#include <platform.h>
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#include <pubsub_events.h>
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#define CPUAMU_NR_COUNTERS 5U
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struct amu_ctx {
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uint64_t cnts[CPUAMU_NR_COUNTERS];
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unsigned int mask;
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};
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static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
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int midr_match(unsigned int cpu_midr)
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{
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unsigned int midr, midr_mask;
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midr = (unsigned int)read_midr();
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midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) |
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(MIDR_PN_MASK << MIDR_PN_SHIFT);
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return ((midr & midr_mask) == (cpu_midr & midr_mask));
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}
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void cpuamu_context_save(unsigned int nr_counters)
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{
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struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
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unsigned int i;
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assert(nr_counters <= CPUAMU_NR_COUNTERS);
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/* Save counter configuration */
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ctx->mask = cpuamu_read_cpuamcntenset_el0();
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/* Disable counters */
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cpuamu_write_cpuamcntenclr_el0(ctx->mask);
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isb();
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/* Save counters */
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for (i = 0; i < nr_counters; i++)
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ctx->cnts[i] = cpuamu_cnt_read(i);
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}
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void cpuamu_context_restore(unsigned int nr_counters)
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{
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struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
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unsigned int i;
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assert(nr_counters <= CPUAMU_NR_COUNTERS);
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/*
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* Disable counters. They were enabled early in the
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* CPU reset function.
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*/
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cpuamu_write_cpuamcntenclr_el0(ctx->mask);
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isb();
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/* Restore counters */
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for (i = 0; i < nr_counters; i++)
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cpuamu_cnt_write(i, ctx->cnts[i]);
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isb();
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/* Restore counter configuration */
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cpuamu_write_cpuamcntenset_el0(ctx->mask);
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}
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