25 lines
710 B
ArmAsm
25 lines
710 B
ArmAsm
/*
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* Copyright (c) 2020, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* The Arm Ltd. FPGA images start execution at address 0x0, which is
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* mapped at an (emulated) ROM image. The payload uploader can write to
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* this memory, but write access by the CPU cores is prohibited.
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*
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* Provide a simple trampoline to start BL31 execution at the actual
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* load address. We put the DTB address in x0, so any code in DRAM could
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* make use of that information (not yet used in BL31 right now).
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*/
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#include <asm_macros.S>
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#include <common/bl_common.ld.h>
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.text
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.global _start
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_start:
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mov_imm x1, BL31_BASE /* beginning of DRAM */
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mov_imm x0, FPGA_PRELOADED_DTB_BASE
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br x1
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