196 lines
6.5 KiB
C
196 lines
6.5 KiB
C
/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef APUPWR_CLKCTL_DEF_H
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#define APUPWR_CLKCTL_DEF_H
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#include <lib/mmio.h>
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enum dvfs_voltage_domain {
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V_VPU0 = 0,
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V_VPU1 = 1,
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V_MDLA0 = 2,
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V_MDLA1 = 3,
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V_APU_CONN = 4,
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V_TOP_IOMMU = 5,
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V_VCORE = 6,
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APUSYS_BUCK_DOMAIN_NUM = 7,
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};
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enum dvfs_freq {
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DVFS_FREQ_NOT_SUPPORT = 0,
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DVFS_FREQ_ACC_26M = 1,
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DVFS_FREQ_ACC_PARKING = 2,
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DVFS_FREQ_ACC_SOC = 3,
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DVFS_FREQ_ACC_APUPLL = 4,
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DVFS_FREQ_00_026000_F = 26000,
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DVFS_FREQ_00_208000_F = 208000,
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DVFS_FREQ_00_238000_F = 238000,
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DVFS_FREQ_00_273000_F = 273000,
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DVFS_FREQ_00_312000_F = 312000,
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DVFS_FREQ_00_358000_F = 358000,
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DVFS_FREQ_00_385000_F = 385000,
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DVFS_FREQ_00_499200_F = 499200,
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DVFS_FREQ_00_500000_F = 500000,
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DVFS_FREQ_00_525000_F = 525000,
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DVFS_FREQ_00_546000_F = 546000,
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DVFS_FREQ_00_594000_F = 594000,
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DVFS_FREQ_00_624000_F = 624000,
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DVFS_FREQ_00_688000_F = 688000,
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DVFS_FREQ_00_687500_F = 687500,
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DVFS_FREQ_00_728000_F = 728000,
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DVFS_FREQ_00_800000_F = 800000,
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DVFS_FREQ_00_832000_F = 832000,
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DVFS_FREQ_00_960000_F = 960000,
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DVFS_FREQ_00_1100000_F = 1100000,
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};
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#define DVFS_FREQ_MAX (DVFS_FREQ_00_1100000_F)
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enum pll_set_rate_mode {
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CON0_PCW = 0,
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FHCTL_SW = 1,
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FHCTL_HW = 2,
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PLL_SET_RATE_MODE_MAX = 3,
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};
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enum apupll {
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APUPLL = 0,
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NPUPLL = 1,
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APUPLL1 = 2,
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APUPLL2 = 3,
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APUPLL_MAX = 4,
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};
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#define BUCK_VVPU_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_273000_F)
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#define BUCK_VMDLA_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_312000_F)
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#define BUCK_VCONN_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_208000_F)
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#define apupwr_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL)
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#define apupwr_writel_relax(VAL, REG) mmio_write_32_relax((uintptr_t)REG, VAL)
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#define apupwr_readl(REG) mmio_read_32((uintptr_t)REG)
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#define apupwr_clrbits(VAL, REG) mmio_clrbits_32((uintptr_t)REG, VAL)
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#define apupwr_setbits(VAL, REG) mmio_setbits_32((uintptr_t)REG, VAL)
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#define apupwr_clrsetbits(CLR_VAL, SET_VAL, REG) \
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mmio_clrsetbits_32((uintptr_t)REG, CLR_VAL, SET_VAL)
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/* PLL and related register */
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#define APU_PLL_BASE (APUSYS_APU_PLL_BASE)
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#define APU_PLL4H_PLL1_CON0 (APU_PLL_BASE + 0x008)
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#define APU_PLL4H_PLL1_CON1 (APU_PLL_BASE + 0x00C)
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#define APU_PLL4H_PLL1_CON3 (APU_PLL_BASE + 0x014)
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#define APU_PLL4H_PLL2_CON0 (APU_PLL_BASE + 0x018)
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#define APU_PLL4H_PLL2_CON1 (APU_PLL_BASE + 0x01C)
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#define APU_PLL4H_PLL2_CON3 (APU_PLL_BASE + 0x024)
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#define APU_PLL4H_PLL3_CON0 (APU_PLL_BASE + 0x028)
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#define APU_PLL4H_PLL3_CON1 (APU_PLL_BASE + 0x02C)
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#define APU_PLL4H_PLL3_CON3 (APU_PLL_BASE + 0x034)
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#define APU_PLL4H_PLL4_CON0 (APU_PLL_BASE + 0x038)
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#define APU_PLL4H_PLL4_CON1 (APU_PLL_BASE + 0x03C)
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#define APU_PLL4H_PLL4_CON3 (APU_PLL_BASE + 0x044)
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#define APU_PLL4H_FHCTL_HP_EN (APU_PLL_BASE + 0x0E00)
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#define APU_PLL4H_FHCTL_UNITSLOPE_EN (APU_PLL_BASE + 0x0E04)
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#define APU_PLL4H_FHCTL_CLK_CON (APU_PLL_BASE + 0x0E08)
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#define APU_PLL4H_FHCTL_RST_CON (APU_PLL_BASE + 0x0E0C)
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#define APU_PLL4H_FHCTL_SLOPE0 (APU_PLL_BASE + 0x0E10)
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#define APU_PLL4H_FHCTL_SLOPE1 (APU_PLL_BASE + 0x0E14)
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#define APU_PLL4H_FHCTL_DSSC_CFG (APU_PLL_BASE + 0x0E18)
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#define APU_PLL4H_FHCTL_DSSC0_CON (APU_PLL_BASE + 0x0E1C)
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#define APU_PLL4H_FHCTL_DSSC1_CON (APU_PLL_BASE + 0x0E20)
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#define APU_PLL4H_FHCTL_DSSC2_CON (APU_PLL_BASE + 0x0E24)
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#define APU_PLL4H_FHCTL_DSSC3_CON (APU_PLL_BASE + 0x0E28)
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#define APU_PLL4H_FHCTL_DSSC4_CON (APU_PLL_BASE + 0x0E2C)
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#define APU_PLL4H_FHCTL_DSSC5_CON (APU_PLL_BASE + 0x0E30)
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#define APU_PLL4H_FHCTL_DSSC6_CON (APU_PLL_BASE + 0x0E34)
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#define APU_PLL4H_FHCTL_DSSC7_CON (APU_PLL_BASE + 0x0E38)
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#define APU_PLL4H_FHCTL0_CFG (APU_PLL_BASE + 0x0E3C)
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#define APU_PLL4H_FHCTL0_UPDNLMT (APU_PLL_BASE + 0x0E40)
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#define APU_PLL4H_FHCTL0_DDS (APU_PLL_BASE + 0x0E44)
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#define APU_PLL4H_FHCTL0_DVFS (APU_PLL_BASE + 0x0E48)
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#define APU_PLL4H_FHCTL0_MON (APU_PLL_BASE + 0x0E4C)
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#define APU_PLL4H_FHCTL1_CFG (APU_PLL_BASE + 0x0E50)
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#define APU_PLL4H_FHCTL1_UPDNLMT (APU_PLL_BASE + 0x0E54)
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#define APU_PLL4H_FHCTL1_DDS (APU_PLL_BASE + 0x0E58)
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#define APU_PLL4H_FHCTL1_DVFS (APU_PLL_BASE + 0x0E5C)
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#define APU_PLL4H_FHCTL1_MON (APU_PLL_BASE + 0x0E60)
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#define APU_PLL4H_FHCTL2_CFG (APU_PLL_BASE + 0x0E64)
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#define APU_PLL4H_FHCTL2_UPDNLMT (APU_PLL_BASE + 0x0E68)
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#define APU_PLL4H_FHCTL2_DDS (APU_PLL_BASE + 0x0E6C)
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#define APU_PLL4H_FHCTL2_DVFS (APU_PLL_BASE + 0x0E70)
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#define APU_PLL4H_FHCTL2_MON (APU_PLL_BASE + 0x0E74)
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#define APU_PLL4H_FHCTL3_CFG (APU_PLL_BASE + 0x0E78)
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#define APU_PLL4H_FHCTL3_UPDNLMT (APU_PLL_BASE + 0x0E7C)
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#define APU_PLL4H_FHCTL3_DDS (APU_PLL_BASE + 0x0E80)
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#define APU_PLL4H_FHCTL3_DVFS (APU_PLL_BASE + 0x0E84)
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#define APU_PLL4H_FHCTL3_MON (APU_PLL_BASE + 0x0E88)
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/* PLL4H_PLLx_CON0 */
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#define RG_PLL_EN BIT(0)
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/* PLL4H_PLLx_CON1 */
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#define RG_PLL_SDM_PCW_CHG BIT(31)
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#define POSDIV_SHIFT (24U)
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#define POSDIV_MASK (0x7)
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/* PLL4H_PLLx_CON3 */
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#define DA_PLL_SDM_PWR_ON BIT(0)
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#define DA_PLL_SDM_ISO_EN BIT(1)
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/* FHCTLx_DDS */
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#define DDS_MASK GENMASK_32(21, 0)
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#define PCW_FRACTIONAL_SHIFT 14U
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#define PLL_TGL_ORG BIT(31)
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#define PLL_READY_TIME_20US (20U)
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#define PLL_CMD_READY_TIME_1US (1U)
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#define FREQ_VCO_MIN (1500U) /* 1500MHz*/
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#define FREQ_FIN (26U) /* 26M*/
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/* ACC and related register */
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#define APU_ACC_BASE (APUSYS_APU_ACC_BASE)
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#define APU_ACC_CONFG_SET0 (APU_ACC_BASE + 0x000)
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#define APU_ACC_CONFG_SET1 (APU_ACC_BASE + 0x004)
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#define APU_ACC_CONFG_SET2 (APU_ACC_BASE + 0x008)
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#define APU_ACC_CONFG_SET4 (APU_ACC_BASE + 0x010)
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#define APU_ACC_CONFG_SET5 (APU_ACC_BASE + 0x014)
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#define APU_ACC_CONFG_SET7 (APU_ACC_BASE + 0x01C)
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#define APU_ACC_CONFG_CLR0 (APU_ACC_BASE + 0x040)
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#define APU_ACC_CONFG_CLR1 (APU_ACC_BASE + 0x044)
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#define APU_ACC_CONFG_CLR2 (APU_ACC_BASE + 0x048)
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#define APU_ACC_CONFG_CLR4 (APU_ACC_BASE + 0x050)
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#define APU_ACC_CONFG_CLR5 (APU_ACC_BASE + 0x054)
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#define APU_ACC_CONFG_CLR7 (APU_ACC_BASE + 0x05C)
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#define APU_ACC_FM_CONFG_SET (APU_ACC_BASE + 0x0C0)
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#define APU_ACC_FM_CONFG_CLR (APU_ACC_BASE + 0x0C4)
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#define APU_ACC_FM_SEL (APU_ACC_BASE + 0x0C8)
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#define APU_ACC_FM_CNT (APU_ACC_BASE + 0x0CC)
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/* APU AO control */
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#define APU_AO_CTRL_BASE (APUSYS_APU_S_S_4_BASE)
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#define APU_CSR_DUMMY_0 (APU_AO_CTRL_BASE + 0x24)
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#define AO_MD32_MNOC_MASK (BIT(1) | BIT(0))
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#define BIT_CGEN_F26M (0)
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#define BIT_CGEN_PARK (1)
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#define BIT_CGEN_SOC (2)
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#define BIT_CGEN_APU (3)
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#define BIT_CGEN_OUT (4)
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#define BIT_SEL_PARK (8)
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#define BIT_SEL_F26M (9)
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#define BIT_SEL_APU_DIV2 (10)
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#define BIT_SEL_APU (11)
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#define BIT_SEL_PARK_SRC_OUT (12)
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#define BIT_INVEN_OUT (15)
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#endif /* APUPWR_CLKCTL_DEF_H*/
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