291 lines
8.5 KiB
C
291 lines
8.5 KiB
C
/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bakery_lock.h>
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#include <mmio.h>
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#include <platform.h>
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#include <arch_helpers.h>
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#include "pm_ipi.h"
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#include "../zynqmp_private.h"
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/* IPI message buffers */
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#define IPI_BUFFER_BASEADDR 0xFF990000U
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#define IPI_BUFFER_RPU_0_BASE (IPI_BUFFER_BASEADDR + 0x0U)
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#define IPI_BUFFER_RPU_1_BASE (IPI_BUFFER_BASEADDR + 0x200U)
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#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U)
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#define IPI_BUFFER_PL_0_BASE (IPI_BUFFER_BASEADDR + 0x600U)
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#define IPI_BUFFER_PL_1_BASE (IPI_BUFFER_BASEADDR + 0x800U)
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#define IPI_BUFFER_PL_2_BASE (IPI_BUFFER_BASEADDR + 0xA00U)
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#define IPI_BUFFER_PL_3_BASE (IPI_BUFFER_BASEADDR + 0xC00U)
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#define IPI_BUFFER_PMU_BASE (IPI_BUFFER_BASEADDR + 0xE00U)
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#define IPI_BUFFER_TARGET_RPU_0_OFFSET 0x0U
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#define IPI_BUFFER_TARGET_RPU_1_OFFSET 0x40U
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#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U
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#define IPI_BUFFER_TARGET_PL_0_OFFSET 0xC0U
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#define IPI_BUFFER_TARGET_PL_1_OFFSET 0x100U
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#define IPI_BUFFER_TARGET_PL_2_OFFSET 0x140U
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#define IPI_BUFFER_TARGET_PL_3_OFFSET 0x180U
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#define IPI_BUFFER_TARGET_PMU_OFFSET 0x1C0U
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#define IPI_BUFFER_MAX_WORDS 8
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#define IPI_BUFFER_REQ_OFFSET 0x0U
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#define IPI_BUFFER_RESP_OFFSET 0x20U
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/* IPI Base Address */
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#define IPI_BASEADDR 0XFF300000
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/* APU's IPI registers */
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#define IPI_APU_ISR (IPI_BASEADDR + 0X00000010)
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#define IPI_APU_IER (IPI_BASEADDR + 0X00000018)
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#define IPI_APU_IDR (IPI_BASEADDR + 0X0000001C)
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#define IPI_APU_IXR_PMU_0_MASK (1 << 16)
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#define IPI_TRIG_OFFSET 0
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#define IPI_OBS_OFFSET 4
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/* Power Management IPI interrupt number */
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#define PM_INT_NUM 0
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#define IPI_PMU_PM_INT_BASE (IPI_PMU_0_TRIG + (PM_INT_NUM * 0x1000))
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#define IPI_PMU_PM_INT_MASK (IPI_APU_IXR_PMU_0_MASK << PM_INT_NUM)
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#if (PM_INT_NUM < 0 || PM_INT_NUM > 3)
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#error PM_INT_NUM value out of range
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#endif
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#define IPI_APU_MASK 1U
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DEFINE_BAKERY_LOCK(pm_secure_lock);
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const struct pm_ipi apu_ipi = {
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.mask = IPI_APU_MASK,
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.base = IPI_BASEADDR,
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.buffer_base = IPI_BUFFER_APU_BASE,
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};
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/**
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* pm_ipi_init() - Initialize IPI peripheral for communication with PMU
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*
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* @return On success, the initialization function must return 0.
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* Any other return value will cause the framework to ignore
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* the service
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*
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* Called from pm_setup initialization function
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*/
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int pm_ipi_init(void)
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{
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bakery_lock_init(&pm_secure_lock);
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/* IPI Interrupts Clear & Disable */
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mmio_write_32(IPI_APU_ISR, 0xffffffff);
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mmio_write_32(IPI_APU_IDR, 0xffffffff);
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return 0;
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}
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/**
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* pm_ipi_wait() - wait for pmu to handle request
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* @proc proc which is waiting for PMU to handle request
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*/
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static enum pm_ret_status pm_ipi_wait(const struct pm_proc *proc)
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{
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int status;
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/* Wait until previous interrupt is handled by PMU */
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do {
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status = mmio_read_32(proc->ipi->base + IPI_OBS_OFFSET) &
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IPI_PMU_PM_INT_MASK;
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/* TODO: 1) Use timer to add delay between read attempts */
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/* TODO: 2) Return PM_RET_ERR_TIMEOUT if this times out */
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} while (status);
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return PM_RET_SUCCESS;
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}
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/**
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* pm_ipi_send_common() - Sends IPI request to the PMU
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* @proc Pointer to the processor who is initiating request
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* @payload API id and call arguments to be written in IPI buffer
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*
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* Send an IPI request to the power controller. Caller needs to hold
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* the 'pm_secure_lock' lock.
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*
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* @return Returns status, either success or error+reason
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*/
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static enum pm_ret_status pm_ipi_send_common(const struct pm_proc *proc,
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uint32_t payload[PAYLOAD_ARG_CNT])
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{
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unsigned int offset = 0;
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uintptr_t buffer_base = proc->ipi->buffer_base +
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IPI_BUFFER_TARGET_PMU_OFFSET +
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IPI_BUFFER_REQ_OFFSET;
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/* Wait until previous interrupt is handled by PMU */
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pm_ipi_wait(proc);
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/* Write payload into IPI buffer */
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for (size_t i = 0; i < PAYLOAD_ARG_CNT; i++) {
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mmio_write_32(buffer_base + offset, payload[i]);
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offset += PAYLOAD_ARG_SIZE;
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}
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/* Generate IPI to PMU */
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mmio_write_32(proc->ipi->base + IPI_TRIG_OFFSET, IPI_PMU_PM_INT_MASK);
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return PM_RET_SUCCESS;
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}
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/**
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* pm_ipi_send() - Sends IPI request to the PMU
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* @proc Pointer to the processor who is initiating request
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* @payload API id and call arguments to be written in IPI buffer
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*
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* Send an IPI request to the power controller.
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*
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* @return Returns status, either success or error+reason
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*/
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enum pm_ret_status pm_ipi_send(const struct pm_proc *proc,
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uint32_t payload[PAYLOAD_ARG_CNT])
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{
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enum pm_ret_status ret;
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bakery_lock_get(&pm_secure_lock);
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ret = pm_ipi_send_common(proc, payload);
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bakery_lock_release(&pm_secure_lock);
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return ret;
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}
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/**
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* pm_ipi_buff_read() - Reads IPI response after PMU has handled interrupt
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* @proc Pointer to the processor who is waiting and reading response
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* @value Used to return value from IPI buffer element (optional)
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* @count Number of values to return in @value
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*
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* @return Returns status, either success or error+reason
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*/
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static enum pm_ret_status pm_ipi_buff_read(const struct pm_proc *proc,
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unsigned int *value, size_t count)
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{
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size_t i;
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uintptr_t buffer_base = proc->ipi->buffer_base +
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IPI_BUFFER_TARGET_PMU_OFFSET +
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IPI_BUFFER_RESP_OFFSET;
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pm_ipi_wait(proc);
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/*
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* Read response from IPI buffer
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* buf-0: success or error+reason
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* buf-1: value
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* buf-2: unused
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* buf-3: unused
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*/
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for (i = 1; i <= count; i++) {
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*value = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE));
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value++;
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}
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return mmio_read_32(buffer_base);
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}
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/**
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* pm_ipi_buff_read_callb() - Reads IPI response after PMU has handled interrupt
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* @value Used to return value from IPI buffer element (optional)
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* @count Number of values to return in @value
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*
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* @return Returns status, either success or error+reason
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*/
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void pm_ipi_buff_read_callb(unsigned int *value, size_t count)
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{
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size_t i;
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uintptr_t buffer_base = IPI_BUFFER_PMU_BASE +
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IPI_BUFFER_TARGET_APU_OFFSET +
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IPI_BUFFER_REQ_OFFSET;
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if (count > IPI_BUFFER_MAX_WORDS)
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count = IPI_BUFFER_MAX_WORDS;
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for (i = 0; i <= count; i++) {
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*value = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE));
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value++;
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}
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}
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/**
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* pm_ipi_send_sync() - Sends IPI request to the PMU
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* @proc Pointer to the processor who is initiating request
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* @payload API id and call arguments to be written in IPI buffer
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* @value Used to return value from IPI buffer element (optional)
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* @count Number of values to return in @value
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*
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* Send an IPI request to the power controller and wait for it to be handled.
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*
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* @return Returns status, either success or error+reason and, optionally,
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* @value
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*/
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enum pm_ret_status pm_ipi_send_sync(const struct pm_proc *proc,
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uint32_t payload[PAYLOAD_ARG_CNT],
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unsigned int *value, size_t count)
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{
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enum pm_ret_status ret;
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bakery_lock_get(&pm_secure_lock);
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ret = pm_ipi_send_common(proc, payload);
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if (ret != PM_RET_SUCCESS)
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goto unlock;
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ret = pm_ipi_buff_read(proc, value, count);
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unlock:
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bakery_lock_release(&pm_secure_lock);
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return ret;
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}
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void pm_ipi_irq_enable(void)
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{
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mmio_write_32(IPI_APU_IER, IPI_APU_IXR_PMU_0_MASK);
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}
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void pm_ipi_irq_disable(void)
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{
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mmio_write_32(IPI_APU_IDR, IPI_APU_IXR_PMU_0_MASK);
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}
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void pm_ipi_irq_clear(void)
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{
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mmio_write_32(IPI_APU_ISR, IPI_APU_IXR_PMU_0_MASK);
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}
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