81 lines
2.5 KiB
ArmAsm
81 lines
2.5 KiB
ArmAsm
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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#include <pmu_sram.h>
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.globl pmu_cpuson_entrypoint_start
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.globl pmu_cpuson_entrypoint_end
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func pmu_cpuson_entrypoint
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pmu_cpuson_entrypoint_start:
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ldr x5, psram_data
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check_wake_cpus:
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mrs x0, MPIDR_EL1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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orr x0, x0, x1
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/* primary_cpu */
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ldr w1, [x5, #PSRAM_DT_MPIDR]
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cmp w0, w1
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b.eq sys_wakeup
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/*
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* If the core is not the primary cpu,
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* force the core into wfe.
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*/
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wfe_loop:
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wfe
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b wfe_loop
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sys_wakeup:
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/* check ddr flag for resume ddr */
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ldr w2, [x5, #PSRAM_DT_DDRFLAG]
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cmp w2, #0x0
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b.eq sys_resume
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ddr_resume:
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ldr x2, [x5, #PSRAM_DT_SP]
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mov sp, x2
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ldr x1, [x5, #PSRAM_DT_DDR_FUNC]
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ldr x0, [x5, #PSRAM_DT_DDR_DATA]
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blr x1
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sys_resume:
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ldr x1, sys_wakeup_entry
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br x1
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.align 3
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psram_data:
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.quad PSRAM_DT_BASE
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sys_wakeup_entry:
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.quad psci_entrypoint
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pmu_cpuson_entrypoint_end:
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.word 0
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endfunc pmu_cpuson_entrypoint
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