d6b798097e
The Cortex-A76 implements SMCCC_ARCH_WORKAROUND_2 as defined in "Firmware interfaces for mitigating cache speculation vulnerabilities System Software on Arm Systems"[0]. Dynamic mitigation for CVE-2018-3639 is enabled/disabled by setting/clearning bit 16 (Disable load pass store) of `CPUACTLR2_EL1`. NOTE: The generic code that implements dynamic mitigation does not currently implement the expected semantics when dispatching an SDEI event to a lower EL. This will be fixed in a separate patch. [0] https://developer.arm.com/cache-speculation-vulnerability-firmware-specification Change-Id: I8fb2862b9ab24d55a0e9693e48e8be4df32afb5a Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> |
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aem_generic.h | ||
cortex_a35.h | ||
cortex_a53.h | ||
cortex_a55.h | ||
cortex_a57.h | ||
cortex_a72.h | ||
cortex_a73.h | ||
cortex_a75.h | ||
cortex_a76.h | ||
cortex_ares.h | ||
cpu_macros.S | ||
cpuamu.h | ||
denver.h |