211 lines
4.4 KiB
C
211 lines
4.4 KiB
C
/*
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* Copyright 2020-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IMX_SEC_DEF_H
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#define IMX_SEC_DEF_H
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/* RDC MDA index */
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enum rdc_mda_idx {
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RDC_MDA_A53 = 0,
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RDC_MDA_M7 = 1,
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RDC_MDA_SDMA3p = 3,
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RDC_MDA_LCDIF = 5,
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RDC_MDA_ISI = 6,
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RDC_MDA_SDMA3b = 7,
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RDC_MDA_Coresight = 8,
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RDC_MDA_DAP = 9,
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RDC_MDA_CAAM = 10,
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RDC_MDA_SDMA1p = 11,
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RDC_MDA_SDMA1b = 12,
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RDC_MDA_APBHDMA = 13,
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RDC_MDA_RAWNAND = 14,
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RDC_MDA_uSDHC1 = 15,
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RDC_MDA_uSDHC2 = 16,
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RDC_MDA_uSDHC3 = 17,
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RDC_MDA_GPU = 18,
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RDC_MDA_USB1 = 19,
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RDC_MDA_TESTPORT = 21,
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RDC_MDA_ENET1_TX = 22,
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RDC_MDA_ENET1_RX = 23,
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RDC_MDA_SDMA2 = 24,
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};
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/* RDC Peripherals index */
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enum rdc_pdap_idx {
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RDC_PDAP_GPIO1 = 0,
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RDC_PDAP_GPIO2 = 1,
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RDC_PDAP_GPIO3 = 2,
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RDC_PDAP_GPIO4 = 3,
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RDC_PDAP_GPIO5 = 4,
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RDC_PDAP_ANA_TSENSOR = 6,
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RDC_PDAP_ANA_OSC = 7,
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RDC_PDAP_WDOG1 = 8,
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RDC_PDAP_WDOG2 = 9,
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RDC_PDAP_WDOG3 = 10,
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RDC_PDAP_SDMA3 = 11,
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RDC_PDAP_SDMA2 = 12,
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RDC_PDAP_GPT1 = 13,
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RDC_PDAP_GPT2 = 14,
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RDC_PDAP_GPT3 = 15,
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RDC_PDAP_ROMCP = 17,
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RDC_PDAP_IOMUXC = 19,
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RDC_PDAP_IOMUXC_GPR = 20,
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RDC_PDAP_OCOTP_CTRL = 21,
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RDC_PDAP_ANA_PLL = 22,
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RDC_PDAP_SNVS_HP = 23,
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RDC_PDAP_CCM = 24,
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RDC_PDAP_SRC = 25,
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RDC_PDAP_GPC = 26,
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RDC_PDAP_SEMAPHORE1 = 27,
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RDC_PDAP_SEMAPHORE2 = 28,
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RDC_PDAP_RDC = 29,
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RDC_PDAP_CSU = 30,
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RDC_PDAP_LCDIF = 32,
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RDC_PDAP_MIPI_DSI = 33,
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RDC_PDAP_ISI = 34,
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RDC_PDAP_MIPI_CSI = 35,
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RDC_PDAP_USB1 = 36,
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RDC_PDAP_PWM1 = 38,
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RDC_PDAP_PWM2 = 39,
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RDC_PDAP_PWM3 = 40,
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RDC_PDAP_PWM4 = 41,
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RDC_PDAP_System_Counter_RD = 42,
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RDC_PDAP_System_Counter_CMP = 43,
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RDC_PDAP_System_Counter_CTRL = 44,
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RDC_PDAP_GPT6 = 46,
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RDC_PDAP_GPT5 = 47,
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RDC_PDAP_GPT4 = 48,
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RDC_PDAP_TZASC = 56,
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RDC_PDAP_PERFMON1 = 60,
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RDC_PDAP_PERFMON2 = 61,
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RDC_PDAP_PLATFORM_CTRL = 62,
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RDC_PDAP_QoSC = 63,
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RDC_PDAP_I2C1 = 66,
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RDC_PDAP_I2C2 = 67,
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RDC_PDAP_I2C3 = 68,
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RDC_PDAP_I2C4 = 69,
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RDC_PDAP_UART4 = 70,
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RDC_PDAP_MU_A = 74,
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RDC_PDAP_MU_B = 75,
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RDC_PDAP_SEMAPHORE_HS = 76,
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RDC_PDAP_SAI2 = 79,
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RDC_PDAP_SAI3 = 80,
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RDC_PDAP_SAI5 = 82,
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RDC_PDAP_SAI6 = 83,
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RDC_PDAP_uSDHC1 = 84,
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RDC_PDAP_uSDHC2 = 85,
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RDC_PDAP_uSDHC3 = 86,
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RDC_PDAP_SAI7 = 87,
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RDC_PDAP_SPBA2 = 90,
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RDC_PDAP_QSPI = 91,
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RDC_PDAP_SDMA1 = 93,
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RDC_PDAP_ENET1 = 94,
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RDC_PDAP_SPDIF1 = 97,
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RDC_PDAP_eCSPI1 = 98,
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RDC_PDAP_eCSPI2 = 99,
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RDC_PDAP_eCSPI3 = 100,
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RDC_PDAP_MICFIL = 101,
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RDC_PDAP_UART1 = 102,
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RDC_PDAP_UART3 = 104,
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RDC_PDAP_UART2 = 105,
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RDC_PDAP_ASRC = 107,
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RDC_PDAP_SPBA1 = 111,
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RDC_PDAP_CAAM = 114,
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};
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enum csu_csl_idx {
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CSU_CSL_GPIO1 = 0,
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CSU_CSL_GPIO2 = 1,
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CSU_CSL_GPIO3 = 2,
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CSU_CSL_GPIO4 = 3,
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CSU_CSL_GPIO5 = 4,
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CSU_CSL_ANA_TSENSOR = 6,
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CSU_CSL_ANA_OSC = 7,
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CSU_CSL_WDOG1 = 8,
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CSU_CSL_WDOG2 = 9,
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CSU_CSL_WDOG3 = 10,
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CSU_CSL_SDMA2 = 12,
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CSU_CSL_GPT1 = 13,
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CSU_CSL_GPT2 = 14,
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CSU_CSL_GPT3 = 15,
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CSU_CSL_ROMCP = 17,
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CSU_CSL_LCDIF = 18,
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CSU_CSL_IOMUXC = 19,
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CSU_CSL_IOMUXC_GPR = 20,
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CSU_CSL_OCOTP_CTRL = 21,
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CSU_CSL_ANA_PLL = 22,
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CSU_CSL_SNVS_HP = 23,
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CSU_CSL_CCM = 24,
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CSU_CSL_SRC = 25,
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CSU_CSL_GPC = 26,
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CSU_CSL_SEMAPHORE1 = 27,
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CSU_CSL_SEMAPHORE2 = 28,
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CSU_CSL_RDC = 29,
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CSU_CSL_CSU = 30,
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CSU_CSL_DC_MST0 = 32,
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CSU_CSL_DC_MST1 = 33,
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CSU_CSL_DC_MST2 = 34,
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CSU_CSL_DC_MST3 = 35,
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CSU_CSL_PWM1 = 38,
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CSU_CSL_PWM2 = 39,
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CSU_CSL_PWM3 = 40,
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CSU_CSL_PWM4 = 41,
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CSU_CSL_System_Counter_RD = 42,
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CSU_CSL_System_Counter_CMP = 43,
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CSU_CSL_System_Counter_CTRL = 44,
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CSU_CSL_GPT6 = 46,
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CSU_CSL_GPT5 = 47,
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CSU_CSL_GPT4 = 48,
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CSU_CSL_TZASC = 56,
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CSU_CSL_MTR = 59,
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CSU_CSL_PERFMON1 = 60,
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CSU_CSL_PERFMON2 = 61,
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CSU_CSL_PLATFORM_CTRL = 62,
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CSU_CSL_QoSC = 63,
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CSU_CSL_MIPI_PHY = 64,
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CSU_CSL_MIPI_DSI = 65,
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CSU_CSL_I2C1 = 66,
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CSU_CSL_I2C2 = 67,
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CSU_CSL_I2C3 = 68,
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CSU_CSL_I2C4 = 69,
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CSU_CSL_UART4 = 70,
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CSU_CSL_MIPI_CSI1 = 71,
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CSU_CSL_MIPI_CSI_PHY1 = 72,
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CSU_CSL_CSI1 = 73,
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CSU_CSL_MU_A = 74,
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CSU_CSL_MU_B = 75,
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CSU_CSL_SEMAPHORE_HS = 76,
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CSU_CSL_SAI1 = 78,
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CSU_CSL_SAI6 = 80,
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CSU_CSL_SAI5 = 81,
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CSU_CSL_SAI4 = 82,
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CSU_CSL_uSDHC1 = 84,
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CSU_CSL_uSDHC2 = 85,
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CSU_CSL_MIPI_CSI2 = 86,
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CSU_CSL_MIPI_CSI_PHY2 = 87,
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CSU_CSL_CSI2 = 88,
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CSU_CSL_SPBA2 = 90,
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CSU_CSL_QSPI = 91,
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CSU_CSL_SDMA1 = 93,
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CSU_CSL_ENET1 = 94,
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CSU_CSL_SPDIF1 = 97,
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CSU_CSL_eCSPI1 = 98,
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CSU_CSL_eCSPI2 = 99,
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CSU_CSL_eCSPI3 = 100,
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CSU_CSL_UART1 = 102,
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CSU_CSL_UART3 = 104,
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CSU_CSL_UART2 = 105,
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CSU_CSL_SPDIF2 = 106,
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CSU_CSL_SAI2 = 107,
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CSU_CSL_SAI3 = 108,
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CSU_CSL_SPBA1 = 111,
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CSU_CSL_CAAM = 114,
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CSU_CSL_OCRAM = 118,
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CSU_CSL_OCRAM_S = 119,
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};
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#endif /* IMX_SEC_DEF_H */
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