110 lines
2.0 KiB
ArmAsm
110 lines
2.0 KiB
ArmAsm
/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include "micro_delay.h"
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#define CPG_BASE (0xE6150000)
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#define CPG_SMSTPCR1 (0x0134)
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#define CPG_CPGWPR (0x0900)
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/* Module bit for TMU ch3-5 */
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#define MSTPCR1_TMU1 (1 << 24)
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#define TMU3_BASE (0xE6FC0000)
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#define TMU_TSTR (0x0004)
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#define TMU_TCOR (0x0008)
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#define TMU_TCNT (0x000C)
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#define TMU_TCR (0x0010)
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/* Start bit for TMU ch3 */
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#define TSTR1_TMU3 (1 << 0)
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#define MIDR_CA57 (0x0D07 << MIDR_PN_SHIFT)
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#define MIDR_CA53 (0x0D03 << MIDR_PN_SHIFT)
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.globl rcar_micro_delay
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#if (TMU3_MEASUREMENT == 1)
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.globl tmu3_init
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.globl tmu3_start
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.globl tmu3_stop
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.globl tcnt3_snapshot
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#endif
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/* Aligned with the cache line */
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.align 6
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func rcar_micro_delay
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cbz x0, micro_delay_e
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mrs x1, midr_el1
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and x1, x1, #MIDR_PN_MASK << MIDR_PN_SHIFT
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mov w2, #MIDR_CA53
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cmp w1, w2
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b.eq micro_delay_ca53
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b micro_delay_ca57
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micro_delay_e:
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ret
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endfunc rcar_micro_delay
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func micro_delay_ca57
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ca57_loop_1:
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mov x1, #185
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ca57_loop_2:
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subs x1, x1, #1
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b.ne ca57_loop_2
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subs x0, x0, #1
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b.ne ca57_loop_1
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ret
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endfunc micro_delay_ca57
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func micro_delay_ca53
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ca53_loop_1:
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mov x1, #134
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ca53_loop_2:
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subs x1, x1, #1
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b.ne ca53_loop_2
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subs x0, x0, #1
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b.ne ca53_loop_1
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ret
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endfunc micro_delay_ca53
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#if (TMU3_MEASUREMENT == 1)
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func tmu3_init
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ldr x2, =CPG_BASE
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ldr w0, [x2, #CPG_SMSTPCR1]
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ldr w1, [x2, #CPG_MSTPSR1]
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ldr w2, #MSTPCR1_TMU1
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bl mstpcr_write
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ret
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endfunc tmu3_init
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func tmu3_start
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ldr x0, =TMU3_BASE
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mov w1, #0xFFFFFFFF
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str w1, [x0, TMU_TCNT]
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ldr x0, =TMU3_BASE
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ldrb w1, [x0, TMU_TSTR]
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orr w1, w1, #TSTR1_TMU3
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strb w1, [x0, TMU_TSTR]
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ret
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endfunc tmu3_start
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func tcnt3_snapshot
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ldr x0, =TMU3_BASE
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ldr w0, [x0, TMU_TCNT]
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ret
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endfunc tcnt3_snapshot
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func tmu3_stop
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ldr x0, =TMU3_BASE
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ldrb w1, [x0, TMU_TSTR]
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and w1, w1, #~TSTR1_TMU3
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strb w1, [x0, TMU_TSTR]
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ret
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endfunc tmu3_stop
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#endif
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