116 lines
4.6 KiB
C
116 lines
4.6 KiB
C
/*
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* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef BOOT_INIT_DRAM_REGDEF_E3_H
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#define BOOT_INIT_DRAM_REGDEF_E3_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#define BIT0 0x00000001U
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#define BIT11 0x00000800U
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#define BIT30 0x40000000U
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/* DBSC registers */
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#define DBSC_E3_DBSYSCONF1 0xE6790004U
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#define DBSC_E3_DBPHYCONF0 0xE6790010U
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#define DBSC_E3_DBKIND 0xE6790020U
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#define DBSC_E3_DBMEMCONF00 0xE6790030U
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#define DBSC_E3_DBSYSCNT0 0xE6790100U
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#define DBSC_E3_DBACEN 0xE6790200U
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#define DBSC_E3_DBRFEN 0xE6790204U
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#define DBSC_E3_DBCMD 0xE6790208U
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#define DBSC_E3_DBWAIT 0xE6790210U
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#define DBSC_E3_DBTR0 0xE6790300U
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#define DBSC_E3_DBTR1 0xE6790304U
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#define DBSC_E3_DBTR2 0xE6790308U
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#define DBSC_E3_DBTR3 0xE679030CU
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#define DBSC_E3_DBTR4 0xE6790310U
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#define DBSC_E3_DBTR5 0xE6790314U
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#define DBSC_E3_DBTR6 0xE6790318U
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#define DBSC_E3_DBTR7 0xE679031CU
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#define DBSC_E3_DBTR8 0xE6790320U
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#define DBSC_E3_DBTR9 0xE6790324U
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#define DBSC_E3_DBTR10 0xE6790328U
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#define DBSC_E3_DBTR11 0xE679032CU
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#define DBSC_E3_DBTR12 0xE6790330U
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#define DBSC_E3_DBTR13 0xE6790334U
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#define DBSC_E3_DBTR14 0xE6790338U
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#define DBSC_E3_DBTR15 0xE679033CU
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#define DBSC_E3_DBTR16 0xE6790340U
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#define DBSC_E3_DBTR17 0xE6790344U
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#define DBSC_E3_DBTR18 0xE6790348U
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#define DBSC_E3_DBTR19 0xE679034CU
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#define DBSC_E3_DBTR20 0xE6790350U
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#define DBSC_E3_DBTR21 0xE6790354U
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#define DBSC_E3_DBBL 0xE6790400U
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#define DBSC_E3_DBRFCNF1 0xE6790414U
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#define DBSC_E3_DBRFCNF2 0xE6790418U
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#define DBSC_E3_DBCALCNF 0xE6790424U
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#define DBSC_E3_DBODT0 0xE6790460U
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#define DBSC_E3_DBADJ0 0xE6790500U
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#define DBSC_E3_DBDFICUPDCNF 0xE679052CU
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#define DBSC_E3_DBDFICNT0 0xE6790604U
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#define DBSC_E3_DBPDLK0 0xE6790620U
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#define DBSC_E3_DBPDRGA0 0xE6790624U
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#define DBSC_E3_DBPDRGD0 0xE6790628U
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#define DBSC_E3_DBBUS0CNF1 0xE6790804U
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#define DBSC_E3_DBCAM0CNF1 0xE6790904U
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#define DBSC_E3_DBCAM0CNF2 0xE6790908U
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#define DBSC_E3_DBCAM0STAT0 0xE6790980U
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#define DBSC_E3_DBBCAMDIS 0xE67909FCU
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#define DBSC_E3_DBSCHCNT0 0xE6791000U
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#define DBSC_E3_DBSCHSZ0 0xE6791010U
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#define DBSC_E3_DBSCHRW0 0xE6791020U
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#define DBSC_E3_DBSCHRW1 0xE6791024U
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#define DBSC_E3_DBSCHQOS00 0xE6791030U
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#define DBSC_E3_DBSCHQOS01 0xE6791034U
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#define DBSC_E3_DBSCHQOS02 0xE6791038U
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#define DBSC_E3_DBSCHQOS03 0xE679103CU
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#define DBSC_E3_DBSCHQOS40 0xE6791070U
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#define DBSC_E3_DBSCHQOS41 0xE6791074U
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#define DBSC_E3_DBSCHQOS42 0xE6791078U
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#define DBSC_E3_DBSCHQOS43 0xE679107CU
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#define DBSC_E3_DBSCHQOS90 0xE67910C0U
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#define DBSC_E3_DBSCHQOS91 0xE67910C4U
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#define DBSC_E3_DBSCHQOS92 0xE67910C8U
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#define DBSC_E3_DBSCHQOS93 0xE67910CCU
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#define DBSC_E3_DBSCHQOS130 0xE6791100U
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#define DBSC_E3_DBSCHQOS131 0xE6791104U
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#define DBSC_E3_DBSCHQOS132 0xE6791108U
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#define DBSC_E3_DBSCHQOS133 0xE679110CU
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#define DBSC_E3_DBSCHQOS140 0xE6791110U
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#define DBSC_E3_DBSCHQOS141 0xE6791114U
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#define DBSC_E3_DBSCHQOS142 0xE6791118U
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#define DBSC_E3_DBSCHQOS143 0xE679111CU
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#define DBSC_E3_DBSCHQOS150 0xE6791120U
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#define DBSC_E3_DBSCHQOS151 0xE6791124U
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#define DBSC_E3_DBSCHQOS152 0xE6791128U
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#define DBSC_E3_DBSCHQOS153 0xE679112CU
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#define DBSC_E3_SCFCTST0 0xE6791700U
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#define DBSC_E3_SCFCTST1 0xE6791708U
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#define DBSC_E3_SCFCTST2 0xE679170CU
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/* CPG registers */
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#define CPG_SRCR4 0xE61500BCU
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#define CPG_PLLECR 0xE61500D0U
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#define CPG_CPGWPR 0xE6150900U
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#define CPG_CPGWPCR 0xE6150904U
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#define CPG_SRSTCLR4 0xE6150950U
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/* MODE Monitor registers */
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#define RST_MODEMR 0xE6160060U
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* BOOT_INIT_DRAM_REGDEF_E3_H */
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