114 lines
3.6 KiB
C
114 lines
3.6 KiB
C
/*
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* Copyright (c) 2017-2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QOS_COMMON_H
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#define QOS_COMMON_H
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#define RCAR_REF_DEFAULT (0U)
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#if (RCAR_LSI == RCAR_E3)
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/* define used for E3 */
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#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */
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#define SUB_SLOT_CYCLE_E3 (0xAFU) /* 175 */
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#else /* REF 7.8usec */
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#define SUB_SLOT_CYCLE_E3 (0x15EU) /* 350 */
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#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
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#define OPERATING_FREQ_E3 (266U) /* MHz */
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#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 -1U)
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#define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) /* unit:ns */
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#endif
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
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/* define used for M3N */
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#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
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#define SUB_SLOT_CYCLE_M3N (0x84U) /* 132 */
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#else /* REF 3.9usec */
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#define SUB_SLOT_CYCLE_M3N (0x108U) /* 264 */
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#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
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#define SL_INIT_SSLOTCLK_M3N (SUB_SLOT_CYCLE_M3N -1U)
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#define QOSWT_WTSET0_CYCLE_M3N ((SUB_SLOT_CYCLE_M3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
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#endif
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
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/* define used for H3 */
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#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
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#define SUB_SLOT_CYCLE_H3_20 (0x84U) /* 132 */
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#else /* REF 3.9usec */
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#define SUB_SLOT_CYCLE_H3_20 (0x108U) /* 264 */
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#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
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#define SL_INIT_SSLOTCLK_H3_20 (SUB_SLOT_CYCLE_H3_20 -1U)
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#define QOSWT_WTSET0_CYCLE_H3_20 ((SUB_SLOT_CYCLE_H3_20 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
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/* define used for H3 Cut 30 */
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#define SUB_SLOT_CYCLE_H3_30 (SUB_SLOT_CYCLE_H3_20) /* same as H3 Cut 20 */
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#define SL_INIT_SSLOTCLK_H3_30 (SUB_SLOT_CYCLE_H3_30 -1U)
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#define QOSWT_WTSET0_CYCLE_H3_30 ((SUB_SLOT_CYCLE_H3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
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#endif
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#if (RCAR_LSI == RCAR_H3N)
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/* define used for H3N */
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#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
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#define SUB_SLOT_CYCLE_H3N (0x84U) /* 132 */
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#else /* REF 3.9usec */
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#define SUB_SLOT_CYCLE_H3N (0x108U) /* 264 */
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#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
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#define SL_INIT_SSLOTCLK_H3N (SUB_SLOT_CYCLE_H3N -1U)
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#define QOSWT_WTSET0_CYCLE_H3N ((SUB_SLOT_CYCLE_H3N * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
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#endif
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#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
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/* define used for M3 */
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#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
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#define SUB_SLOT_CYCLE_M3_11 (0x84U) /* 132 */
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#else /* REF 3.9usec */
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#define SUB_SLOT_CYCLE_M3_11 (0x108U) /* 264 */
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#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
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#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 -1U)
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#define QOSWT_WTSET0_CYCLE_M3_11 ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
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#endif
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#define OPERATING_FREQ (400U) /* MHz */
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#define BASE_SUB_SLOT_NUM (0x6U)
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#define SUB_SLOT_CYCLE (0x7EU) /* 126 */
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#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
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#define SL_INIT_REFFSSLOT (0x3U << 24U)
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#define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U)
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#define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE -1U)
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static inline void io_write_32(uintptr_t addr, uint32_t value)
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{
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*(volatile uint32_t *)addr = value;
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}
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static inline uint32_t io_read_32(uintptr_t addr)
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{
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return *(volatile uint32_t *)addr;
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}
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static inline void io_write_64(uintptr_t addr, uint64_t value)
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{
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*(volatile uint64_t *)addr = value;
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}
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typedef struct {
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uintptr_t addr;
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uint64_t value;
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} mstat_slot_t;
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extern uint32_t qos_init_ddr_ch;
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extern uint8_t qos_init_ddr_phyvalid;
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#endif /* QOS_COMMON_H */
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