136 lines
5.1 KiB
C
136 lines
5.1 KiB
C
/*
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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#include "../zynqmp_def.h"
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#define PLATFORM_STACK_SIZE 0x440
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#define PLATFORM_CORE_COUNT 4
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#define PLAT_NUM_POWER_DOMAINS 5
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#define PLAT_MAX_PWR_LVL 1
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 2
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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#define ZYNQMP_BL31_SIZE 0x1b000
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/*
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* Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL31 debug size plus a
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* little space for growth.
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*/
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#if ZYNQMP_ATF_LOCATION_ID == ZYNQMP_IN_TRUSTED_SRAM
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# define BL31_BASE (ZYNQMP_TRUSTED_SRAM_LIMIT - \
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ZYNQMP_BL31_SIZE)
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# define BL31_PROGBITS_LIMIT (ZYNQMP_TRUSTED_SRAM_LIMIT - 0x6000)
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# define BL31_LIMIT ZYNQMP_TRUSTED_SRAM_LIMIT
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#elif ZYNQMP_ATF_LOCATION_ID == ZYNQMP_IN_TRUSTED_DRAM
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# define BL31_BASE (ZYNQMP_TRUSTED_DRAM_LIMIT - \
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ZYNQMP_BL31_SIZE)
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# define BL31_PROGBITS_LIMIT (ZYNQMP_TRUSTED_DRAM_LIMIT - 0x6000)
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# define BL31_LIMIT (ZYNQMP_TRUSTED_DRAM_BASE + \
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ZYNQMP_TRUSTED_DRAM_SIZE)
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#else
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# error "Unsupported ZYNQMP_ATF_LOCATION_ID value"
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#endif
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/*******************************************************************************
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* BL32 specific defines.
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******************************************************************************/
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/*
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* On ZYNQMP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
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*/
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#if ZYNQMP_TSP_RAM_LOCATION_ID == ZYNQMP_IN_TRUSTED_SRAM
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# define TSP_SEC_MEM_BASE ZYNQMP_TRUSTED_SRAM_BASE
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# define TSP_SEC_MEM_SIZE ZYNQMP_TRUSTED_SRAM_SIZE
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# define TSP_PROGBITS_LIMIT (ZYNQMP_TRUSTED_SRAM_LIMIT - \
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ZYNQMP_BL31_SIZE)
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# define BL32_BASE ZYNQMP_TRUSTED_SRAM_BASE
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# define BL32_LIMIT (ZYNQMP_TRUSTED_SRAM_LIMIT - \
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ZYNQMP_BL31_SIZE)
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#elif ZYNQMP_TSP_RAM_LOCATION_ID == ZYNQMP_IN_TRUSTED_DRAM
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# define TSP_SEC_MEM_BASE ZYNQMP_TRUSTED_DRAM_BASE
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# define TSP_SEC_MEM_SIZE (ZYNQMP_TRUSTED_DRAM_LIMIT - \
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ZYNQMP_BL31_SIZE)
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# define BL32_BASE ZYNQMP_TRUSTED_DRAM_BASE
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# define BL32_LIMIT (ZYNQMP_TRUSTED_DRAM_LIMIT - \
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ZYNQMP_BL31_SIZE)
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#else
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# error "Unsupported ZYNQMP_TSP_RAM_LOCATION_ID value"
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#endif
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/*
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* ID of the secure physical generic timer interrupt used by the TSP.
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*/
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#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_XLAT_TABLES 5
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#define MAX_MMAP_REGIONS 7
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \
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IRQ_SEC_IPI_APU, \
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ARM_IRQ_SEC_SGI_0, \
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ARM_IRQ_SEC_SGI_1, \
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ARM_IRQ_SEC_SGI_2, \
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ARM_IRQ_SEC_SGI_3, \
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ARM_IRQ_SEC_SGI_4, \
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ARM_IRQ_SEC_SGI_5, \
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ARM_IRQ_SEC_SGI_6, \
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ARM_IRQ_SEC_SGI_7
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#define PLAT_ARM_G0_IRQS
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#endif /* __PLATFORM_DEF_H__ */
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