181 lines
5.4 KiB
C
181 lines
5.4 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <denver.h>
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#include <errno.h>
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#include <mce.h>
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#include <memctrl.h>
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#include <runtime_svc.h>
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#include <t18x_ari.h>
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#include <tegra_private.h>
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extern uint32_t tegra186_system_powerdn_state;
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/*******************************************************************************
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* Offset to read the ref_clk counter value
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******************************************************************************/
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#define REF_CLK_OFFSET 4
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/*******************************************************************************
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* Tegra186 SiP SMCs
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******************************************************************************/
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#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0xC2FFFE01
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#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02
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#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00
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#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01
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#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02
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#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03
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#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04
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#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05
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#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06
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#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07
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#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08
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#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09
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#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0xC2FFFF0A
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#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0xC2FFFF0B
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#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0xC2FFFF0C
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#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0xC2FFFF0D
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#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0xC2FFFF0E
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#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0xC2FFFF0F
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#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0xC2FFFF10
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#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0xC2FFFF11
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#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0xC2FFFF12
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/*******************************************************************************
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* This function is responsible for handling all T186 SiP calls
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******************************************************************************/
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int plat_sip_handler(uint32_t smc_fid,
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uint64_t x1,
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uint64_t x2,
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uint64_t x3,
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uint64_t x4,
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void *cookie,
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void *handle,
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uint64_t flags)
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{
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int mce_ret;
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int impl, cpu;
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uint32_t base, core_clk_ctr, ref_clk_ctr;
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if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
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/* 32-bit function, clear top parameter bits */
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x1 = (uint32_t)x1;
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x2 = (uint32_t)x2;
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x3 = (uint32_t)x3;
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}
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/*
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* Convert SMC FID to SMC64, to support SMC32/SMC64 configurations
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*/
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smc_fid |= (SMC_64 << FUNCID_CC_SHIFT);
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switch (smc_fid) {
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/*
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* Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 -
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* 0x82FFFFFF SiP SMC space
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*/
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case TEGRA_SIP_MCE_CMD_ENTER_CSTATE:
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case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO:
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case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME:
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case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS:
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case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS:
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case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED:
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case TEGRA_SIP_MCE_CMD_CC3_CTRL:
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case TEGRA_SIP_MCE_CMD_ECHO_DATA:
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case TEGRA_SIP_MCE_CMD_READ_VERSIONS:
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case TEGRA_SIP_MCE_CMD_ENUM_FEATURES:
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case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
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case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA:
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case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA:
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case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE:
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case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE:
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case TEGRA_SIP_MCE_CMD_ENABLE_LATIC:
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case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ:
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case TEGRA_SIP_MCE_CMD_MISC_CCPLEX:
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/* clean up the high bits */
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smc_fid &= MCE_CMD_MASK;
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/* execute the command and store the result */
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mce_ret = mce_command_handler(smc_fid, x1, x2, x3);
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0,
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(uint64_t)mce_ret);
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return 0;
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case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE:
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/* clean up the high bits */
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x1 = (uint32_t)x1;
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/*
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* SC8 is a special Tegra186 system state where the CPUs and
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* DRAM are powered down but the other subsystem is still
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* alive.
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*/
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if ((x1 == TEGRA_ARI_SYSTEM_SC8) ||
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(x1 == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF)) {
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tegra186_system_powerdn_state = x1;
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flush_dcache_range(
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(uintptr_t)&tegra186_system_powerdn_state,
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sizeof(tegra186_system_powerdn_state));
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} else {
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ERROR("%s: unhandled powerdn state (%d)\n", __func__,
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(uint32_t)x1);
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return -ENOTSUP;
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}
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return 0;
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/*
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* This function ID reads the Activity monitor's core/ref clock
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* counter values for a core/cluster.
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*
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* x1 = MPIDR of the target core
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* x2 = MIDR of the target core
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*/
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case TEGRA_SIP_GET_ACTMON_CLK_COUNTERS:
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cpu = (uint32_t)x1 & MPIDR_CPU_MASK;
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impl = ((uint32_t)x2 >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
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/* sanity check target CPU number */
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if (cpu > PLATFORM_MAX_CPUS_PER_CLUSTER)
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return -EINVAL;
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/* get the base address for the current CPU */
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base = (impl == DENVER_IMPL) ? TEGRA_DENVER_ACTMON_CTR_BASE :
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TEGRA_ARM_ACTMON_CTR_BASE;
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/* read the clock counter values */
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core_clk_ctr = mmio_read_32(base + (8 * cpu));
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ref_clk_ctr = mmio_read_32(base + (8 * cpu) + REF_CLK_OFFSET);
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/* return the counter values as two different parameters */
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1,
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(uint64_t)core_clk_ctr);
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write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2,
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(uint64_t)ref_clk_ctr);
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return 0;
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default:
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break;
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}
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return -ENOTSUP;
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}
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