93 lines
1.8 KiB
ArmAsm
93 lines
1.8 KiB
ArmAsm
/*
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* Copyright 2018-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <platform_def.h>
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.globl plat_secondary_cold_boot_setup
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.globl plat_is_my_cpu_primary
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.globl plat_reset_handler
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.globl platform_mem_init
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func platform_mem1_init
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ret
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endfunc platform_mem1_init
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func platform_mem_init
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ret
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endfunc platform_mem_init
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func l2_mem_init
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/* Initialize the L2 RAM latency */
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mrs x1, S3_1_c11_c0_2
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mov x0, #0x1C7
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/* Clear L2 Tag RAM latency and L2 Data RAM latency */
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bic x1, x1, x0
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/* Set L2 data ram latency bits [2:0] */
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orr x1, x1, #0x2
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/* set L2 tag ram latency bits [8:6] */
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orr x1, x1, #0x80
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msr S3_1_c11_c0_2, x1
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isb
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ret
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endfunc l2_mem_init
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func apply_platform_errata
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ret
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endfunc apply_platform_errata
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func plat_reset_handler
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mov x29, x30
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#if (defined(IMAGE_BL2) && BL2_AT_EL3)
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bl l2_mem_init
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#endif
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bl apply_platform_errata
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#if defined(IMAGE_BL31)
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ldr x0, =POLICY_SMMU_PAGESZ_64K
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cbz x0, 1f
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/* Set the SMMU page size in the SACR register */
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bl _set_smmu_pagesz_64
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#endif
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1:
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/*
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* May be cntfrq_el0 needs to be assigned
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* the value COUNTER_FREQUENCY
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*/
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mov x30, x29
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ret
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endfunc plat_reset_handler
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/*
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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*/
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func plat_secondary_cold_boot_setup
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/* ls1046a does not do cold boot for secondary CPU */
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cb_panic:
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b cb_panic
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endfunc plat_secondary_cold_boot_setup
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/*
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary cpu.
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, 0x0
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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