126 lines
3.3 KiB
C
126 lines
3.3 KiB
C
/*
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* Copyright 2018-2022 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef SOC_H
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#define SOC_H
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/* Chassis specific defines - common across SoC's of a particular platform */
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#include <dcfg_lsch2.h>
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#include <soc_default_base_addr.h>
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#include <soc_default_helper_macros.h>
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/* DDR Regions Info */
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#define NUM_DRAM_REGIONS U(3)
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#define NXP_DRAM0_ADDR ULL(0x80000000)
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#define NXP_DRAM0_MAX_SIZE ULL(0x80000000) /* 2 GB */
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#define NXP_DRAM1_ADDR ULL(0x880000000)
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#define NXP_DRAM1_MAX_SIZE ULL(0x780000000) /* 30 GB */
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#define NXP_DRAM2_ADDR ULL(0x8800000000)
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#define NXP_DRAM2_MAX_SIZE ULL(0x7800000000) /* 480 GB */
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/*DRAM0 Size defined in platform_def.h */
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#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE
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/*
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* SVR Definition (not include major and minor rev)
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* A: without security
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* AE: with security
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*/
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#define SVR_LS1026A 0x870709
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#define SVR_LS1026AE 0x870708
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#define SVR_LS1046A 0x870701
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#define SVR_LS1046AE 0x870700
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/* Number of cores in platform */
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/* Used by common code for array initialization */
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#define NUMBER_OF_CLUSTERS U(1)
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#define CORES_PER_CLUSTER U(4)
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#define PLATFORM_CORE_COUNT (NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER)
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/*
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* Required LS standard platform porting definitions
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* for CCI-400
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*/
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#define NXP_CCI_CLUSTER0_SL_IFACE_IX 4
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/* Defines required for using XLAT tables from ARM common code */
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40)
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/* Clock Divisors */
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#define NXP_PLATFORM_CLK_DIVIDER U(1)
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#define NXP_UART_CLK_DIVIDER U(2)
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/* set to 0 if the clusters are not symmetrical */
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#define SYMMETRICAL_CLUSTERS U(1)
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/*
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* set this switch to 1 if you need to keep the debug block
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* clocked during system power-down
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*/
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#define DEBUG_ACTIVE 0
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/*
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* pwr mgmt features supported in the soc-specific code:
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* value == 0x0 the soc code does not support this feature
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* value != 0x0 the soc code supports this feature
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*/
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#define SOC_CORE_RELEASE 0x1
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#define SOC_CORE_RESTART 0x1
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#define SOC_CORE_OFF 0x1
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#define SOC_CORE_STANDBY 0x1
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#define SOC_CORE_PWR_DWN 0x1
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#define SOC_CLUSTER_STANDBY 0x1
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#define SOC_CLUSTER_PWR_DWN 0x1
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#define SOC_SYSTEM_STANDBY 0x1
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#define SOC_SYSTEM_PWR_DWN 0x1
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#define SOC_SYSTEM_OFF 0x1
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#define SOC_SYSTEM_RESET 0x1
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/* Start: Macros used by lib/psci files */
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#define SYSTEM_PWR_DOMAINS 1
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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NUMBER_OF_CLUSTERS + \
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SYSTEM_PWR_DOMAINS)
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/* Power state coordination occurs at the system level */
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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/* define retention state */
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#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1)
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/* define power-down state */
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#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*
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* CACHE_WRITEBACK_GRANULE is defined in soc.def
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*/
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/* One cache line needed for bakery locks on ARM platforms */
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#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
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#ifndef __ASSEMBLER__
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/* CCI slave interfaces */
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static const int cci_map[] = {
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NXP_CCI_CLUSTER0_SL_IFACE_IX,
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};
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void soc_init_lowlevel(void);
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void soc_init_percpu(void);
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void _soc_set_start_addr(unsigned long addr);
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#endif
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#endif /* SOC_H */
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