256d133a8a
- Flag GICV2_G0_FOR_EL3 needs to be set for group interrupts to be targeted to EL3. - Raise SGI interrupts for individual CPU cores as GIC API uses CPU num as parameter, not CPU mask. - Flag WARMBOOT_ENABLE_DCACHE_EARLY needs to be set to enable CPU interface mask work properly for all CPU cores which is required when generating SGI. - Call plat_ic_end_of_interrupt() from ttc_fiq_handler() to clear GIC interrupt to avoid same interrupt again. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Change-Id: I71d4935b8d4688a3729c62753ca8a1a77cd92ae7 |
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pm_api_clock.c | ||
pm_api_clock.h | ||
pm_api_ioctl.c | ||
pm_api_ioctl.h | ||
pm_api_pinctrl.c | ||
pm_api_pinctrl.h | ||
pm_api_sys.c | ||
pm_api_sys.h | ||
pm_client.c | ||
pm_client.h | ||
pm_defs.h | ||
pm_svc_main.c | ||
pm_svc_main.h |