Achin Gupta a0cd989dd5 Factor out translation table setup in ARM FVP port ... This patch factors out the ARM FVP specific code to create MMU translation tables so that it is possible for a boot loader stage to create a different set of tables instead of using the default ones. The default translation tables are created with the assumption that the calling boot loader stage executes out of secure SRAM. This might not be true for the BL3_2 stage in the future. A boot loader stage can define the `fill_xlation_tables()` function as per its requirements. It returns a reference to the level 1 translation table which is used by the common platform code to setup the TTBR_EL3. This patch is a temporary solution before a larger rework of translation table creation logic is introduced. Change-Id: I09a075d5da16822ee32a411a9dbe284718fb4ff6		2014-02-20 19:06:34 +00:00
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aarch64	Add exception vector guards	2014-02-20 19:06:34 +00:00
bl1.ld.S	Factor out translation table setup in ARM FVP port	2014-02-20 19:06:34 +00:00
bl1.mk	Factor out translation table setup in ARM FVP port	2014-02-20 19:06:34 +00:00
bl1_main.c	Rework BL2 to BL3-1 hand over interface	2014-02-20 19:06:34 +00:00