142 lines
4.2 KiB
C
142 lines
4.2 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOC_H
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#define SOC_H
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enum plls_id {
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ABPLL_ID = 0,
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ALPLL_ID,
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DPLL_ID,
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CPLL_ID,
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GPLL_ID,
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NPLL_ID,
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END_PLL_ID,
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};
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/*****************************************************************************
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* secure timer
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*****************************************************************************/
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#define TIMER_LOADE_COUNT0 0x00
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#define TIMER_LOADE_COUNT1 0x04
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#define TIMER_CURRENT_VALUE0 0x08
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#define TIMER_CURRENT_VALUE1 0x0C
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#define TIMER_CONTROL_REG 0x10
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#define TIMER_INTSTATUS 0x18
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#define TIMER_EN 0x1
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#define STIMER1_BASE (STIME_BASE + 0x20)
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#define CYCL_24M_CNT_US(us) (24 * us)
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#define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000))
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/*****************************************************************************
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* sgrf reg, offset
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*****************************************************************************/
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#define SGRF_SOC_CON(n) (0x0 + (n) * 4)
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#define SGRF_BUSDMAC_CON(n) (0x100 + (n) * 4)
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#define SGRF_SOC_CON_NS 0xffff0000
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/*****************************************************************************
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* con6[2]pmusram is security.
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* con6[6]stimer is security.
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*****************************************************************************/
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#define PMUSRAM_S_SHIFT 2
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#define PMUSRAM_S 1
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#define STIMER_S_SHIFT 6
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#define STIMER_S 1
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#define SGRF_SOC_CON7_BITS ((0xffffu << 16) | \
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(PMUSRAM_S << PMUSRAM_S_SHIFT) | \
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(STIMER_S << STIMER_S_SHIFT))
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#define SGRF_BUSDMAC_CON0_NS 0xfffcfff8
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#define SGRF_BUSDMAC_CON1_NS 0xffff0fff
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/*
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* sgrf_soc_con1~2, mask and offset
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*/
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#define CPU_BOOT_ADDR_WMASK 0xffff0000
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#define CPU_BOOT_ADDR_ALIGN 16
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/*****************************************************************************
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* cru reg, offset
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*****************************************************************************/
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#define CRU_SOFTRST_CON 0x300
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#define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4))
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#define CRU_SOFTRSTS_CON_CNT 15
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#define SOFTRST_DMA1 0x40004
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#define SOFTRST_DMA2 0x10001
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#define RST_DMA1_MSK 0x4
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#define RST_DMA2_MSK 0x0
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#define CRU_CLKSEL_CON 0x100
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#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4))
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#define CRU_CLKSEL_CON_CNT 56
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#define CRU_CLKGATE_CON 0x200
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#define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
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#define CRU_CLKGATES_CON_CNT 25
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#define CRU_GLB_SRST_FST 0x280
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#define CRU_GLB_SRST_SND 0x284
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#define CRU_GLB_RST_CON 0x388
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#define CRU_CONS_GATEID(i) (16 * (i))
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#define GATE_ID(reg, bit) ((reg * 16) + bit)
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#define PMU_RST_BY_SECOND_SFT (BIT(1) << 2)
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#define PMU_RST_NOT_BY_SFT (BIT(1) << 2)
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/***************************************************************************
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* pll
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***************************************************************************/
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#define PLL_PWR_DN_MSK (0x1 << 1)
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#define PLL_PWR_DN REG_WMSK_BITS(1, 1, 0x1)
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#define PLL_PWR_ON REG_WMSK_BITS(0, 1, 0x1)
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#define PLL_RESET REG_WMSK_BITS(1, 5, 0x1)
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#define PLL_RESET_RESUME REG_WMSK_BITS(0, 5, 0x1)
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#define PLL_BYPASS_MSK (0x1 << 0)
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#define PLL_BYPASS_W_MSK (PLL_BYPASS_MSK << 16)
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#define PLL_BYPASS REG_WMSK_BITS(1, 0, 0x1)
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#define PLL_NO_BYPASS REG_WMSK_BITS(0, 0, 0x1)
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#define PLL_MODE_SHIFT 8
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#define PLL_MODE_MSK 0x3
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#define PLLS_MODE_WMASK (PLL_MODE_MSK << (16 + PLL_MODE_SHIFT))
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#define PLL_SLOW 0x0
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#define PLL_NORM 0x1
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#define PLL_DEEP 0x2
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#define PLL_SLOW_BITS REG_WMSK_BITS(PLL_SLOW, 8, 0x3)
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#define PLL_NORM_BITS REG_WMSK_BITS(PLL_NORM, 8, 0x3)
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#define PLL_DEEP_BITS REG_WMSK_BITS(PLL_DEEP, 8, 0x3)
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#define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
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#define REG_W_MSK(bits_shift, msk) \
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((msk) << ((bits_shift) + 16))
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#define REG_VAL_CLRBITS(val, bits_shift, msk) \
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(val & (~(msk << bits_shift)))
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#define REG_SET_BITS(bits, bits_shift, msk) \
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(((bits) & (msk)) << (bits_shift))
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#define REG_WMSK_BITS(bits, bits_shift, msk) \
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(REG_W_MSK(bits_shift, msk) | \
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REG_SET_BITS(bits, bits_shift, msk))
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#define regs_updata_bit_set(addr, shift) \
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regs_updata_bits((addr), 0x1, 0x1, (shift))
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#define regs_updata_bit_clr(addr, shift) \
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regs_updata_bits((addr), 0x0, 0x1, (shift))
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void regs_updata_bits(uintptr_t addr, uint32_t val,
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uint32_t mask, uint32_t shift);
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void soc_sleep_config(void);
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void pm_plls_resume(void);
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#endif /* SOC_H */
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