148 lines
5.0 KiB
C
148 lines
5.0 KiB
C
/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arm_def.h>
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#include <board_arm_def.h>
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#include <common_def.h>
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#include <tzc400.h>
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#include <v2m_def.h>
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#include "../fvp_def.h"
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/* Required platform porting definitions */
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#define PLAT_NUM_PWR_DOMAINS (ARM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
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/*
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* Other platform porting definitions are provided by included headers
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*/
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/*
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* Required ARM standard platform porting definitions
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*/
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#define PLAT_ARM_CLUSTER0_CORE_COUNT 4
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#define PLAT_ARM_CLUSTER1_CORE_COUNT 4
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#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000
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#define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
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#define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000
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#define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */
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/* No SCP in FVP */
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#define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x0)
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#define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x780000000)
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#define PLAT_ARM_SHARED_RAM_CACHED 1
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/*
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* Load address of BL33 for this platform port
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*/
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#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000)
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/*
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* PL011 related constants
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*/
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#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE
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#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
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#define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE
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#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
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#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE
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#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ
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#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE
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#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ
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/* CCI related constants */
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#define PLAT_ARM_CCI_BASE 0x2c090000
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#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3
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#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4
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/* System timer related constants */
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#define PLAT_ARM_NSTIMER_FRAME_ID 1
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/* Mailbox base address */
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#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
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/* TrustZone controller related constants
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*
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* Currently only filters 0 and 2 are connected on Base FVP.
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* Filter 0 : CPU clusters (no access to DRAM by default)
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* Filter 1 : not connected
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* Filter 2 : LCDs (access to VRAM allowed by default)
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* Filter 3 : not connected
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* Programming unconnected filters will have no effect at the
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* moment. These filter could, however, be connected in future.
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* So care should be taken not to configure the unused filters.
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*
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* Allow only non-secure access to all DRAM to supported devices.
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* Give access to the CPUs and Virtio. Some devices
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* would normally use the default ID so allow that too.
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*/
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#define PLAT_ARM_TZC_BASE 0x2a4a0000
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#define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT(0)
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#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD))
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/*
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* GIC related constants to cater for both GICv2 and GICv3 instances of an
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* FVP. They could be overriden at runtime in case the FVP implements the legacy
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* VE memory map.
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*/
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#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
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#define PLAT_ARM_GICR_BASE BASE_GICR_BASE
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#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \
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FVP_IRQ_TZ_WDOG, \
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FVP_IRQ_SEC_SYS_TIMER
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#define PLAT_ARM_G0_IRQS ARM_G0_IRQS
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#endif /* __PLATFORM_DEF_H__ */
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