68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
/*
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* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <drivers/arm/smmu_v3.h>
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#include <lib/fconf/fconf.h>
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#include <plat/arm/common/arm_config.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include "fvp_private.h"
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uintptr_t hw_config_dtb;
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void __init bl31_early_platform_setup2(u_register_t arg0,
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u_register_t arg1, u_register_t arg2, u_register_t arg3)
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{
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arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
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/* Initialize the platform config for future decision making */
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fvp_config_setup();
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/*
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* Initialize the correct interconnect for this cluster during cold
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* boot. No need for locks as no other CPU is active.
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*/
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fvp_interconnect_init();
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/*
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* Enable coherency in interconnect for the primary CPU's cluster.
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* Earlier bootloader stages might already do this (e.g. Trusted
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* Firmware's BL1 does it) but we can't assume so. There is no harm in
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* executing this code twice anyway.
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* FVP PSCI code will enable coherency for other clusters.
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*/
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fvp_interconnect_enable();
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/* Initialize System level generic or SP804 timer */
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fvp_timer_init();
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/* On FVP RevC, initialize SMMUv3 */
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if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U)
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smmuv3_init(PLAT_FVP_SMMUV3_BASE);
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hw_config_dtb = arg2;
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}
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void __init bl31_plat_arch_setup(void)
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{
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arm_bl31_plat_arch_setup();
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/*
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* For RESET_TO_BL31 systems, BL31 is the first bootloader to run.
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* So there is no BL2 to load the HW_CONFIG dtb into memory before
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* control is passed to BL31.
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*/
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#if !RESET_TO_BL31 && !BL2_AT_EL3
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assert(hw_config_dtb != 0U);
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INFO("BL31 FCONF: HW_CONFIG address = %p\n", (void *)hw_config_dtb);
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fconf_populate("HW_CONFIG", hw_config_dtb);
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#endif
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}
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