185 lines
4.9 KiB
C
185 lines
4.9 KiB
C
/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include "dram_sub_func.h"
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#define PRR (0xFFF00044U)
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#define PRR_PRODUCT_MASK (0x00007F00U)
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#define PRR_CUT_MASK (0x000000FFU)
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#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
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#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
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#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
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#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
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#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */
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#if RCAR_SYSTEM_SUSPEND
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/* Local defines */
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#define DRAM_BACKUP_GPIO_USE (0)
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#include "iic_dvfs.h"
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#if PMIC_ROHM_BD9571
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#define PMIC_SLAVE_ADDR (0x30U)
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#define PMIC_BKUP_MODE_CNT (0x20U)
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#define PMIC_QLLM_CNT (0x27U)
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#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4U))
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#define BIT_QLLM_DDR0_EN ((uint8_t)(1U << 0U))
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#define BIT_QLLM_DDR1_EN ((uint8_t)(1U << 1U))
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#endif
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#define GPIO_OUTDT1 (0xE6051008U)
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#define GPIO_INDT1 (0xE605100CU)
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#define GPIO_OUTDT3 (0xE6053008U)
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#define GPIO_INDT3 (0xE605300CU)
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#define GPIO_OUTDT6 (0xE6055408U)
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#define GPIO_INDT6 (0xE605540CU)
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#if DRAM_BACKUP_GPIO_USE == 1
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#define GPIO_BKUP_REQB_SHIFT_SALVATOR (9U) /* GP1_9 (BKUP_REQB) */
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#define GPIO_BKUP_REQB_SHIFT_EBISU (14U) /* GP6_14(BKUP_REQB) */
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#define GPIO_BKUP_REQB_SHIFT_CONDOR (1U) /* GP3_1 (BKUP_REQB) */
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#endif
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#define GPIO_BKUP_TRG_SHIFT_SALVATOR (8U) /* GP1_8 (BKUP_TRG) */
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#define GPIO_BKUP_TRG_SHIFT_EBISU (13U) /* GP6_13(BKUP_TRG) */
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#define GPIO_BKUP_TRG_SHIFT_CONDOR (0U) /* GP3_0 (BKUP_TRG) */
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#define DRAM_BKUP_TRG_LOOP_CNT (1000U)
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#endif
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void rcar_dram_get_boot_status(uint32_t * status)
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{
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#if RCAR_SYSTEM_SUSPEND
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uint32_t reg_data;
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uint32_t product;
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uint32_t shift;
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uint32_t gpio;
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product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
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if (product == PRR_PRODUCT_V3H) {
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shift = GPIO_BKUP_TRG_SHIFT_CONDOR;
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gpio = GPIO_INDT3;
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} else if (product == PRR_PRODUCT_E3) {
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shift = GPIO_BKUP_TRG_SHIFT_EBISU;
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gpio = GPIO_INDT6;
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} else {
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shift = GPIO_BKUP_TRG_SHIFT_SALVATOR;
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gpio = GPIO_INDT1;
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}
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reg_data = mmio_read_32(gpio);
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if (0U != (reg_data & ((uint32_t)1U << shift))) {
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*status = DRAM_BOOT_STATUS_WARM;
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} else {
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*status = DRAM_BOOT_STATUS_COLD;
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}
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#else /* RCAR_SYSTEM_SUSPEND */
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*status = DRAM_BOOT_STATUS_COLD;
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#endif /* RCAR_SYSTEM_SUSPEND */
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}
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int32_t rcar_dram_update_boot_status(uint32_t status)
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{
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int32_t ret = 0;
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#if RCAR_SYSTEM_SUSPEND
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uint32_t reg_data;
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#if PMIC_ROHM_BD9571
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#if DRAM_BACKUP_GPIO_USE == 0
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uint8_t bkup_mode_cnt = 0U;
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#else
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uint32_t reqb, outd;
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#endif
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uint8_t qllm_cnt = 0U;
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int32_t i2c_dvfs_ret = -1;
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#endif
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uint32_t loop_count;
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uint32_t product;
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uint32_t trg;
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uint32_t gpio;
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product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
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if (product == PRR_PRODUCT_V3H) {
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#if DRAM_BACKUP_GPIO_USE == 1
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reqb = GPIO_BKUP_REQB_SHIFT_CONDOR;
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outd = GPIO_OUTDT3;
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#endif
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trg = GPIO_BKUP_TRG_SHIFT_CONDOR;
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gpio = GPIO_INDT3;
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} else if (product == PRR_PRODUCT_E3) {
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#if DRAM_BACKUP_GPIO_USE == 1
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reqb = GPIO_BKUP_REQB_SHIFT_EBISU;
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outd = GPIO_OUTDT6;
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#endif
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trg = GPIO_BKUP_TRG_SHIFT_EBISU;
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gpio = GPIO_INDT6;
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} else {
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#if DRAM_BACKUP_GPIO_USE == 1
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reqb = GPIO_BKUP_REQB_SHIFT_SALVATOR;
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outd = GPIO_OUTDT1;
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#endif
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trg = GPIO_BKUP_TRG_SHIFT_SALVATOR;
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gpio = GPIO_INDT1;
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}
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if (status == DRAM_BOOT_STATUS_WARM) {
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#if DRAM_BACKUP_GPIO_USE==1
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mmio_setbits_32(outd, 1U << reqb);
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#else
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#if PMIC_ROHM_BD9571
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/* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */
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i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR,
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PMIC_BKUP_MODE_CNT, &bkup_mode_cnt);
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if (0 != i2c_dvfs_ret) {
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ERROR("BKUP mode cnt READ ERROR.\n");
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ret = DRAM_UPDATE_STATUS_ERR;
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} else {
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bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT;
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i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
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PMIC_BKUP_MODE_CNT, bkup_mode_cnt);
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if (0 != i2c_dvfs_ret) {
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ERROR("BKUP mode cnt WRITE ERROR. "
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"value = %d\n", bkup_mode_cnt);
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ret = DRAM_UPDATE_STATUS_ERR;
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}
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}
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#endif /* PMIC_ROHM_BD9571 */
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#endif /* DRAM_BACKUP_GPIO_USE==1 */
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/* Wait BKUP_TRG=Low */
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loop_count = DRAM_BKUP_TRG_LOOP_CNT;
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while (0U < loop_count) {
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reg_data = mmio_read_32(gpio);
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if ((reg_data &
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((uint32_t)1U << trg)) == 0U) {
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break;
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}
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loop_count--;
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}
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if (0U == loop_count) {
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ERROR( "\nWarm booting...\n" \
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" The potential of BKUP_TRG did not switch " \
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"to Low.\n If you expect the operation of " \
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"cold boot,\n check the board configuration" \
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" (ex, Dip-SW) and/or the H/W failure.\n");
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ret = DRAM_UPDATE_STATUS_ERR;
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}
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}
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#if PMIC_ROHM_BD9571
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if(0 == ret) {
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qllm_cnt = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
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i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
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PMIC_QLLM_CNT, qllm_cnt);
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if (0 != i2c_dvfs_ret) {
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ERROR("QLLM cnt WRITE ERROR. "
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"value = %d\n", qllm_cnt);
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ret = DRAM_UPDATE_STATUS_ERR;
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}
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}
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#endif
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#endif
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return ret;
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}
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