101 lines
4.4 KiB
C
101 lines
4.4 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __CORTEX_A57_H__
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#define __CORTEX_A57_H__
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#include <utils_def.h>
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/* Cortex-A57 midr for revision 0 */
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#define CORTEX_A57_MIDR 0x410FD070
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/* Retention timer tick definitions */
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#define RETENTION_ENTRY_TICKS_2 0x1
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#define RETENTION_ENTRY_TICKS_8 0x2
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#define RETENTION_ENTRY_TICKS_32 0x3
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#define RETENTION_ENTRY_TICKS_64 0x4
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#define RETENTION_ENTRY_TICKS_128 0x5
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#define RETENTION_ENTRY_TICKS_256 0x6
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#define RETENTION_ENTRY_TICKS_512 0x7
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_ECTLR p15, 1, c15
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#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
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#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
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#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
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#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
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#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0
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#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
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/*******************************************************************************
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* CPU Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_CPUMERRSR p15, 2, c15
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_CPUACTLR p15, 0, c15
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#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
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#define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
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#define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
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#define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52)
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#define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
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#define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
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#define CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38)
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#define CORTEX_A57_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
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#define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27)
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#define CORTEX_A57_CPUACTLR_DIS_L1_STREAMING (ULL(3) << 25)
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#define CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
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/*******************************************************************************
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* L2 Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
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#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
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#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
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#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
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#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
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/*******************************************************************************
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* L2 Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3
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#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0
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#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A57_L2MERRSR p15, 3, c15
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#if !ERROR_DEPRECATED
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/*
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* These registers were previously wrongly named. Provide previous definitions so
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* as not to break platforms that continue using them.
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*/
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#define CORTEX_A57_ACTLR CORTEX_A57_CPUACTLR
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#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB
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#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE
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#define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_DIS_OVERREAD
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#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
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#define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_DCC_AS_DCCI
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#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
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#define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_DIS_STREAMING
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#define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_DIS_L1_STREAMING
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#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR
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#endif /* !ERROR_DEPRECATED */
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#endif /* __CORTEX_A57_H__ */
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