c3e8b0be9b
This patch changes implementation for disabling Secure Cycle Counter. For ARMv8.5 the counter gets disabled by setting SDCR.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR.DP bit. In 'include\aarch32\arch.h' header file new ARMv8.5-PMU related definitions were added. Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> |
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aarch32 | ||
sp_min.ld.S | ||
sp_min.mk | ||
sp_min_main.c | ||
sp_min_private.h | ||
wa_cve_2017_5715_bpiall.S | ||
wa_cve_2017_5715_icache_inv.S |